From patchwork Tue Oct 6 13:06:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 11818571 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6F206CB for ; Tue, 6 Oct 2020 12:33:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85777206F7 for ; Tue, 6 Oct 2020 12:33:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85777206F7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AEFF6E486; Tue, 6 Oct 2020 12:33:14 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 265F36E483 for ; Tue, 6 Oct 2020 12:33:13 +0000 (UTC) IronPort-SDR: OJ/4zE1Rz+0jWrRFNLBCf4YwcbZ7527WEFpiUf/nzwiSxxU8qxjeeps+07q8IyQLxtyIwiru4+ 015DKmog1XVg== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="161851687" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="161851687" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 05:33:12 -0700 IronPort-SDR: tHA2YTCkcGw20MlhBazlW3S8xwLo69ZlESzULzZiXyG/D1SSEfHMGH8Pg52XEwfJA9f+X9Go03 T9oxMhjg+3Tg== X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="527333636" Received: from unknown (HELO linux-desktop.iind.intel.com) ([10.223.34.173]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 05:33:10 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 18:36:45 +0530 Message-Id: <20201006130654.331-2-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006130654.331-1-uma.shankar@intel.com> References: <20201006130654.331-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v7 01/10] drm/i915/display: Add HDR Capability detection for LSPCON X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES DPCD register. LSPCON implementations capable of supporting HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch reads the same, detects the HDR capability and adds this to intel_lspcon struct. v2: Addressed Jani Nikula's review comment and fixed the HDR capability detection logic Signed-off-by: Uma Shankar --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_lspcon.c | 30 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d5dc18cb8c39..fb8cfc0981d6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1398,6 +1398,7 @@ struct intel_lspcon { bool active; enum drm_lspcon_mode mode; enum lspcon_vendor vendor; + bool hdr_supported; }; struct intel_digital_port { diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index ee95fc353a56..f92962195698 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -35,6 +35,8 @@ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 #define LSPCON_VENDOR_MCA_OUI 0x0060AD +#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 + /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF @@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) return true; } +static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_digital_port *intel_dig_port = + container_of(lspcon, struct intel_digital_port, lspcon); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* Enable HDR for MCA based LSPCON devices */ + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, + &hdr_caps, 1); + else + return; + + if (ret < 0) { + drm_dbg_kms(dev, "hdr capability detection failed\n"); + lspcon->hdr_supported = false; + return; + } else if (hdr_caps & 0x1) { + drm_dbg_kms(dev, "lspcon capable of HDR\n"); + lspcon->hdr_supported = true; + } +} + static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) { enum drm_lspcon_mode current_mode; @@ -554,6 +582,8 @@ static bool lspcon_init(struct intel_digital_port *dig_port) return false; } + lspcon_detect_hdr_capability(lspcon); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n");