From patchwork Wed Oct 21 13:31:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11849129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FF8FC388F9 for ; Wed, 21 Oct 2020 13:32:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C8182080A for ; Wed, 21 Oct 2020 13:32:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C8182080A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A3616EB15; Wed, 21 Oct 2020 13:32:32 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D42A6EB15 for ; Wed, 21 Oct 2020 13:32:30 +0000 (UTC) IronPort-SDR: kxfwWIeepIgGKCi3gUZK+P8n140dF7m78KHWCG2e+OG0MOuVMEotRB7wrF5qsYp48/65Owog9Z UJ4F2kbB1xFA== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="154317762" X-IronPort-AV: E=Sophos;i="5.77,401,1596524400"; d="scan'208";a="154317762" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2020 06:32:30 -0700 IronPort-SDR: E8IDCJfKSopRboTEkXDe7On88CE4JHeG6ZrsPPdLiLpBrVrfkLwj1itpLFUy4ZkN7q+jdMADYi mkXT5VgB5PZg== X-IronPort-AV: E=Sophos;i="5.77,401,1596524400"; d="scan'208";a="316372476" Received: from snadathu-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.252.137.153]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2020 06:32:29 -0700 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Oct 2020 06:31:59 -0700 Message-Id: <20201021133213.328994-5-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201021133213.328994-1-aditya.swarup@intel.com> References: <20201021133213.328994-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce ADLS DDI and HPD masks for setting up hpd interrupts. Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa Signed-off-by: Aditya Swarup Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b753c77c9a77..9033221995ad 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) return; - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) || - HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) + if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) || + HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) || + HAS_PCH_MCC(dev_priv)) hpd->pch_hpd = hpd_icp; else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) hpd->pch_hpd = hpd_spt; @@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) u32 ddi_hotplug_trigger, tc_hotplug_trigger; u32 pin_mask = 0, long_mask = 0; - if (HAS_PCH_TGP(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS; + tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; + } else if (HAS_PCH_TGP(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; } else if (HAS_PCH_JSP(dev_priv)) { @@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) TGP_DDI_HPD_ENABLE_MASK, 0); } +static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv) +{ + icp_hpd_irq_setup(dev_priv, + ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK); +} + static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; @@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (I915_HAS_HOTPLUG(dev_priv)) dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; } else { - if (HAS_PCH_JSP(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup; + else if (HAS_PCH_JSP(dev_priv)) dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; else if (HAS_PCH_MCC(dev_priv)) dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 83ddea1cd174..f6b844ca7a9f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8343,6 +8343,7 @@ enum { SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ SDE_TC_HOTPLUG_ICP(PORT_TC1)) +#define SDE_DDI_MASK_ADLS SDE_DDI_HOTPLUG_ICP(PORT_A) #define SDEISR _MMIO(0xc4000) #define SDEIMR _MMIO(0xc4004) @@ -8438,6 +8439,8 @@ enum { ICP_TC_HPD_ENABLE(PORT_TC5) | \ ICP_TC_HPD_ENABLE_MASK) +#define ADLS_DDI_HPD_ENABLE_MASK SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A) + #define _PCH_DPLL_A 0xc6014 #define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)