From patchwork Wed Nov 25 00:31:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11930027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ED42C2D0E4 for ; Wed, 25 Nov 2020 00:31:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 188822151B for ; Wed, 25 Nov 2020 00:31:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 188822151B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 874A46E7D4; Wed, 25 Nov 2020 00:31:17 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8390F6E7D4 for ; Wed, 25 Nov 2020 00:31:16 +0000 (UTC) IronPort-SDR: LXw3f+e8YSLT08H8IYBMJPE1bHF/Q1F41rOmwKLk3EOaoAHIpSe7Sq8s5z78F1dJV+1fV5rCtA XiiY3UuVdtxQ== X-IronPort-AV: E=McAfee;i="6000,8403,9815"; a="159806745" X-IronPort-AV: E=Sophos;i="5.78,367,1599548400"; d="scan'208";a="159806745" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2020 16:31:15 -0800 IronPort-SDR: 1+ZmE+jWvjV9v6q46O2S8C1DsGKoe5mNUofs//jszGzTROs6TudkDBTEW0IjdxPuRR9fdq3sFl GDJLLHIwt8Mg== X-IronPort-AV: E=Sophos;i="5.78,367,1599548400"; d="scan'208";a="332761683" Received: from mnazaret-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.102.137]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2020 16:31:15 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Tue, 24 Nov 2020 16:31:08 -0800 Message-Id: <20201125003108.156110-1-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Fix TGL REVID macros to fetch correct display/gt stepping based on SOC rev id from INTEL_REVID() macro. Previously, we were just returning the first element of the revid array instead of using the correct index based on SOC rev id. Also, add array bound checks for TGL REV ID array. Since, there might be a possibility of using older kernels on latest platform revision, resulting in out of bounds access for rev ID array. In this scenario, print message for unsupported rev ID and apply settings for latest rev ID available. Fixes: ("drm/i915/tgl: Fix stepping WA matching") Cc: José Roberto de Souza Cc: Matt Roper Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: Aditya Swarup Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/gpu/drm/i915/i915_drv.h | 35 +++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 15be8debae54..29d55b7017be 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1572,16 +1572,37 @@ enum { TGL_REVID_D0, }; -extern const struct i915_rev_steppings tgl_uy_revids[]; -extern const struct i915_rev_steppings tgl_revids[]; +extern const struct i915_rev_steppings tgl_uy_revids[4]; +extern const struct i915_rev_steppings tgl_revids[2]; + +#define TGL_UY_REVID_RANGE(revid) \ + ((revid) < ARRAY_SIZE(tgl_uy_revids)) + +#define TGL_REVID_RANGE(revid) \ + ((revid) < ARRAY_SIZE(tgl_revids)) static inline const struct i915_rev_steppings * tgl_revids_get(struct drm_i915_private *dev_priv) { - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) - return tgl_uy_revids; - else - return tgl_revids; + const u8 revid = INTEL_REVID(dev_priv); + + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { + if (TGL_UY_REVID_RANGE(revid)) { + return tgl_uy_revids + revid; + } else { + drm_dbg_kms(&dev_priv->drm, + "Unsupported SOC stepping found %u, using %lu instead\n", + revid, ARRAY_SIZE(tgl_uy_revids) - 1); + return tgl_uy_revids + (ARRAY_SIZE(tgl_uy_revids) - 1); + } + } else if (TGL_REVID_RANGE(revid)) { + return tgl_revids + revid; + } else { + drm_dbg_kms(&dev_priv->drm, + "Unsupported SOC stepping found %u, using %lu instead\n", + revid, ARRAY_SIZE(tgl_revids) - 1); + return tgl_uy_revids + (ARRAY_SIZE(tgl_revids) - 1); + } } #define IS_TGL_DISP_REVID(p, since, until) \ @@ -1591,12 +1612,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv) #define IS_TGL_UY_GT_REVID(p, since, until) \ ((IS_TGL_U(p) || IS_TGL_Y(p)) && \ + TGL_UY_REVID_RANGE(INTEL_REVID(p)) && \ tgl_uy_revids->gt_stepping >= (since) && \ tgl_uy_revids->gt_stepping <= (until)) #define IS_TGL_GT_REVID(p, since, until) \ (IS_TIGERLAKE(p) && \ !(IS_TGL_U(p) || IS_TGL_Y(p)) && \ + TGL_REVID_RANGE(INTEL_REVID(p)) && \ tgl_revids->gt_stepping >= (since) && \ tgl_revids->gt_stepping <= (until))