From patchwork Thu Dec 3 23:53:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9849C433FE for ; Thu, 3 Dec 2020 23:51:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 559EA22285 for ; Thu, 3 Dec 2020 23:51:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 559EA22285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 071F76E0E5; Thu, 3 Dec 2020 23:51:08 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id E083C6E0DD for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: zdbkA1Erbr6mUaq/lxnrOA0oUehxn9phw9QGFkWbmOwulglghen10CzXQP/lqtCWDd8BkfWmv/ u123MN7qFU5w== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067207" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067207" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: hEHrkBAgwR5tm0pVls17zx4Eetdr0UtzAFnlzHvLhiLgcvrxbxdzXzDLo6cmLGSr1UnKGkI+S0 MLtgXa1AGmkw== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716502" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:54 -0800 Message-Id: <20201203235358.18041-5-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 5/9] drm/i915/display/vrr: Configure and enable VRR in modeset enable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch computes the VRR parameters from VRR crtc states and configures them in VRR registers during CRTC enable in the modeset enable sequence. v2: * Remove initialization to 0 (Jani N) * Use correct pipe %c (Jani N) Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 33 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++ 3 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5193473c838c..48467c6abb37 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -50,6 +50,7 @@ #include "intel_sprite.h" #include "intel_tc.h" #include "intel_vdsc.h" +#include "intel_vrr.h" struct ddi_buf_trans { u32 trans1; /* balance leg enable, de-emph level */ @@ -4245,6 +4246,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state, if (!crtc_state->bigjoiner_slave) intel_ddi_enable_transcoder_func(encoder, crtc_state); + intel_vrr_enable(encoder, crtc_state); + intel_enable_pipe(crtc_state); intel_crtc_vblank_on(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 09dcf6f1c4d9..9dec01695773 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -81,3 +81,36 @@ intel_vrr_compute_config(struct intel_dp *intel_dp, crtc_state->vrr.vtotalmax); } +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + u32 trans_vrr_ctl; + u16 framestart_to_pipelinefull_linecnt; + + if (!crtc_state->vrr.enable) + return; + + framestart_to_pipelinefull_linecnt = + min_t(u16, 255, (crtc_state->vrr.vtotalmin - adjusted_mode->crtc_vdisplay - 4)); + + trans_vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_IGN_MAX_SHIFT | + VRR_CTL_FLIP_LINE_EN | VRR_CTL_LINE_COUNT(framestart_to_pipelinefull_linecnt) | + VRR_CTL_SW_FULLLINE_COUNT; + + intel_de_write(dev_priv, TRANS_VRR_VMIN(pipe), crtc_state->vrr.vtotalmin - 2); + intel_de_write(dev_priv, TRANS_VRR_VMAX(pipe), crtc_state->vrr.vtotalmax - 1); + intel_de_write(dev_priv, TRANS_VRR_CTL(pipe), trans_vrr_ctl); + intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(pipe), crtc_state->vrr.vtotalmin - 1); + intel_de_write(dev_priv, TRANS_PUSH(pipe), TRANS_PUSH_EN); + + drm_dbg_kms(&dev_priv->drm, "Enabling VRR on pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, "VRR Parameters: Vtotal Min = %d, Max = %d Flipline Count = %d, CTL Reg = 0x%08x, TRANS PUSH reg = 0x%08x", + crtc_state->vrr.vtotalmin - 1, crtc_state->vrr.vtotalmax, + crtc_state->vrr.vtotalmin, trans_vrr_ctl, + TRANS_PUSH_EN); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 3f08c32d1afe..97bbbfb4c33b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -13,10 +13,13 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_dp; +struct intel_encoder; bool intel_vrr_is_capable(struct drm_connector *connector); void intel_vrr_check_modeset(struct intel_atomic_state *state); void intel_vrr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */