@@ -49,6 +49,7 @@
#include "intel_psr.h"
#include "intel_dsi.h"
#include "intel_sprite.h"
+#include "intel_vrr.h"
int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
int usecs)
@@ -98,6 +99,13 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
VBLANK_EVASION_TIME_US);
max = vblank_start - 1;
+ /* In case of VRR, we stall the Push and updates if too close to Vmax */
+ if (new_crtc_state->vrr.enable) {
+ min = new_crtc_state->vrr.vtotalmax - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ max = new_crtc_state->vrr.vtotalmax - 1;
+ }
+
if (min <= 0 || max <= 0)
goto irq_disable;
@@ -257,6 +265,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
local_irq_enable();
+ /* Send VRR Push to terminate Vblank */
+ intel_vrr_send_push(new_crtc_state);
+
if (intel_vgpu_active(dev_priv))
return;
@@ -114,3 +114,22 @@ void intel_vrr_enable(struct intel_encoder *encoder,
crtc_state->vrr.vtotalmin, trans_vrr_ctl,
TRANS_PUSH_EN);
}
+
+void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 trans_push;
+
+ if (!crtc_state->vrr.enable)
+ return;
+
+ trans_push = intel_de_read(dev_priv, TRANS_PUSH(pipe));
+ trans_push |= TRANS_PUSH_SEND;
+ intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push);
+ drm_WARN_ON(&dev_priv->drm, !(trans_push & TRANS_PUSH_EN));
+
+ drm_dbg_kms(&dev_priv->drm, "Sending VRR Push on pipe %c\n",
+ pipe_name(pipe));
+}
@@ -21,5 +21,6 @@ void intel_vrr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
void intel_vrr_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VRR_H__ */
VRR achieves vblank stretching using the HW PUSH functionality. So once the VRR is enabled during modeset then for each flip request from userspace, in the atomic tail pipe_update_end() we need to set the VRR push bit in HW for it to terminate the vblank at configured flipline or anytime after flipline or latest at the Vmax. Also in case of VRR, we need to stall the double buffer updates and PUSH if too close to the Vmax. The HW clears the PUSH bit after the double buffer updates are completed. v2: * Move send push to after irq en (Manasi) * Call send push unconditionally (Jani N) v3: * Stall w.r.t Vrr vmax (Manasi, Gary Smith) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gary Smith <gary.k.smith@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++++++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 31 insertions(+)