| Message ID | 20210127041159.136409-4-aditya.swarup@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Final set of patches for ADLS enabling | expand |
On 1/26/21 8:11 PM, Aditya Swarup wrote: > From: Lucas De Marchi <lucas.demarchi@intel.com> > > TGL power wells can be re-used for ADL-S with the exception of the fake > power well for TC_COLD, just like DG-1. > > Bspec: 53597 > > Cc: Imre Deak <imre.deak@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Aditya Swarup <aditya.swarup@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Aditya > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 708f0b7e0990..cccfd45a67cf 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) > * The enabling order will be from lower to higher indexed wells, > * the disabling order is reversed. > */ > - if (IS_DG1(dev_priv)) { > + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { > err = set_power_wells_mask(power_domains, tgl_power_wells, > BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); > } else if (IS_ROCKETLAKE(dev_priv)) { >
On Tue, Jan 26, 2021 at 08:11:53PM -0800, Aditya Swarup wrote: > From: Lucas De Marchi <lucas.demarchi@intel.com> > > TGL power wells can be re-used for ADL-S with the exception of the fake > power well for TC_COLD, just like DG-1. > > Bspec: 53597 I think the bspec reference should actually be page 49231. But aside from that, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > Cc: Imre Deak <imre.deak@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Aditya Swarup <aditya.swarup@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 708f0b7e0990..cccfd45a67cf 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) > * The enabling order will be from lower to higher indexed wells, > * the disabling order is reversed. > */ > - if (IS_DG1(dev_priv)) { > + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { > err = set_power_wells_mask(power_domains, tgl_power_wells, > BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); > } else if (IS_ROCKETLAKE(dev_priv)) { > -- > 2.27.0 >
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 708f0b7e0990..cccfd45a67cf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) {