From patchwork Wed Jan 27 16:54:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12050575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52503C433DB for ; Wed, 27 Jan 2021 16:53:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5DF164D99 for ; Wed, 27 Jan 2021 16:53:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5DF164D99 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 34FDE6E85B; Wed, 27 Jan 2021 16:53:00 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 313976E85A for ; Wed, 27 Jan 2021 16:52:58 +0000 (UTC) IronPort-SDR: OtKCDmkqhEbBfs4RCtLtdks9hVXhtl3fa6VQjbnjgL9u63nLOQD/NlNqp5M3VEQTRRWlg0RDaE cx6I7bMkEPGA== X-IronPort-AV: E=McAfee;i="6000,8403,9877"; a="180176959" X-IronPort-AV: E=Sophos;i="5.79,380,1602572400"; d="scan'208";a="180176959" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2021 08:52:57 -0800 IronPort-SDR: py2vYacTbKw1pcCUFGS+a5aGXepqjy16o3UKWOEznn1vcveyx9cAv6tpPhbetHwHk81bN6kY3i vxBdVOfTGxZQ== X-IronPort-AV: E=Sophos;i="5.79,380,1602572400"; d="scan'208";a="578211832" Received: from reynol4x-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.255.78.69]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2021 08:52:56 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jan 2021 08:54:01 -0800 Message-Id: <20210127165402.117829-3-jose.souza@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210127165402.117829-1-jose.souza@intel.com> References: <20210127165402.117829-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/4] drm/i915: Fail driver probe when unable to load DRAM information X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DRAM information is required to properly program display. Before "drm/i915/gen11+: Only load DRAM information from pcode" we were failing driver load if unable to fetch DRAM information from pcode form GEN11+ but we should also extend it to GEN9 plaforms. Signed-off-by: José Roberto de Souza Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_drv.c | 6 +++++- drivers/gpu/drm/i915/intel_dram.c | 13 +++++++++---- drivers/gpu/drm/i915/intel_dram.h | 2 +- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index aec0e870dc25..7ff58ea30c7c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -622,12 +622,16 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) * Fill the dram structure to get the system dram info. This will be * used for memory latency calculation. */ - intel_dram_detect(dev_priv); + ret = intel_dram_detect(dev_priv); + if (ret) + goto err_dram; intel_bw_init_hw(dev_priv); return 0; +err_dram: + intel_gvt_driver_remove(dev_priv); err_msi: if (pdev->msi_enabled) pci_disable_msi(pdev); diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 4d5ab206eacb..6ce56eedaf12 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -484,7 +484,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915) return icl_pcode_read_mem_global_info(i915); } -void intel_dram_detect(struct drm_i915_private *i915) +int intel_dram_detect(struct drm_i915_private *i915) { struct dram_info *dram_info = &i915->dram_info; int ret; @@ -497,7 +497,7 @@ void intel_dram_detect(struct drm_i915_private *i915) dram_info->is_16gb_dimm = !IS_GEN9_LP(i915); if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915)) - return; + return 0; if (INTEL_GEN(i915) >= 12) ret = gen12_get_dram_info(i915); @@ -507,13 +507,18 @@ void intel_dram_detect(struct drm_i915_private *i915) ret = bxt_get_dram_info(i915); else ret = skl_get_dram_info(i915); - if (ret) - return; + + if (ret) { + drm_warn(&i915->drm, "Unable to load dram information\n"); + return ret; + } drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels); drm_dbg_kms(&i915->drm, "DRAM 16Gb DIMMs: %s\n", yesno(dram_info->is_16gb_dimm)); + + return 0; } static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap) diff --git a/drivers/gpu/drm/i915/intel_dram.h b/drivers/gpu/drm/i915/intel_dram.h index 4ba13c13162c..2a0f283b1a1d 100644 --- a/drivers/gpu/drm/i915/intel_dram.h +++ b/drivers/gpu/drm/i915/intel_dram.h @@ -9,6 +9,6 @@ struct drm_i915_private; void intel_dram_edram_detect(struct drm_i915_private *i915); -void intel_dram_detect(struct drm_i915_private *i915); +int intel_dram_detect(struct drm_i915_private *i915); #endif /* __INTEL_DRAM_H__ */