diff mbox series

drm/i915: Add link rate and lane count to i915_display_info

Message ID 20210205064531.3158292-1-khaled.almahallawy@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Add link rate and lane count to i915_display_info | expand

Commit Message

Almahallawy, Khaled Feb. 5, 2021, 6:45 a.m. UTC 
Link rate and lane count information are more easier and faster to check in i915_display_info
than checking kernel logs for people not familiar with i915 in the following scenarios:
* Debugging DP tunnel bandwidth usage in Thunderbolt driver.
* In USB4 certification, it is a requirement to know which link rate used by
  monitor to prove that DP tunnel handle up to HBR3
* In PHY Compliance, when the connector propes are not mounted correctly,
  some display lanes will not show up in the DP Oscilloscope and will fail CTS.
  Just give the tester an easy way to identify where the problem is.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
CC: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d62b18d5ecd8..c6161c1e87e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -990,9 +990,10 @@  static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
 			   yesno(crtc_state->hw.active),
 			   DRM_MODE_ARG(&crtc_state->hw.adjusted_mode));
 
-		seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d\n",
+		seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d, link rate = %d, lane count = %d\n",
 			   crtc_state->pipe_src_w, crtc_state->pipe_src_h,
-			   yesno(crtc_state->dither), crtc_state->pipe_bpp);
+			   yesno(crtc_state->dither), crtc_state->pipe_bpp,
+			   crtc_state->port_clock, crtc_state->lane_count);
 
 		intel_scaler_info(m, crtc);
 	}