From patchwork Tue Feb 9 18:14:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12078771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AF60C433DB for ; Tue, 9 Feb 2021 18:13:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D26564E3F for ; Tue, 9 Feb 2021 18:13:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9D26564E3F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28F646EB91; Tue, 9 Feb 2021 18:13:28 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 847056EB92 for ; Tue, 9 Feb 2021 18:13:27 +0000 (UTC) IronPort-SDR: 26ok/s3NJ/A6RWCSdBPR5wIK1/KV3de9Wunz10ir2ve9t1mHat/NbrR/ztLyzw5VRIjFqtYO2L KRb2XPPGrSWg== X-IronPort-AV: E=McAfee;i="6000,8403,9890"; a="201014108" X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="201014108" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:25 -0800 IronPort-SDR: oUOsSKnbl4h3l3+hKcnqlPrR2iW3kBsG7CSkI43yB2CxfbcXpC/Bnv4y2E545TgBUWnPbte1R0 2gjGxE+1eTvA== X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="396324686" Received: from rmahmood-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.190.123]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:23 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Feb 2021 10:14:38 -0800 Message-Id: <20210209181439.215104-3-jose.souza@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209181439.215104-1-jose.souza@intel.com> References: <20210209181439.215104-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: Remove some redundancy around CAN_PSR() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If source_support is set the platform supports PSR so no need to check it again at every CAN_PSR(). Also removing the intel_dp_is_edp() calls, if sink_support is set the sink connected is for sure a eDP panel. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display_types.h | 5 ++--- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ebaa9d0ed376..4a46c4e9b0ac 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1793,9 +1793,8 @@ dp_to_i915(struct intel_dp *intel_dp) return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); } -#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && \ - (intel_dp)->psr.sink_support && \ - (intel_dp)->psr.source_support) +#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ + (intel_dp)->psr.source_support) static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4f89e0de5dde..0a0cc61344c4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2358,7 +2358,7 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, return false; } - if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) { + if (CAN_PSR(intel_dp)) { drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n"); crtc_state->uapi.mode_changed = true; return false; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8ad9fcff3a12..e0111b470570 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1962,7 +1962,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | DP_PSR_LINK_CRC_ERROR; - if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp)) + if (!CAN_PSR(intel_dp)) return; mutex_lock(&psr->lock); @@ -2012,7 +2012,7 @@ bool intel_psr_enabled(struct intel_dp *intel_dp) { bool ret; - if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp)) + if (!CAN_PSR(intel_dp)) return false; mutex_lock(&intel_dp->psr.lock);