From patchwork Fri Feb 12 18:21:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12085865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE65FC433E6 for ; Fri, 12 Feb 2021 18:20:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8177A64DDF for ; Fri, 12 Feb 2021 18:20:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8177A64DDF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 550CE6EEA6; Fri, 12 Feb 2021 18:20:44 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2ADCE6E1D8 for ; Fri, 12 Feb 2021 18:20:43 +0000 (UTC) IronPort-SDR: aI8VWkrwuk9BYdZjZcapA7jnP3e/ju9zDdEj94qs7WnPo78KVtDRo8dzZ1lqZlNJOf0UMQnz6W fFVbZx50mH9g== X-IronPort-AV: E=McAfee;i="6000,8403,9893"; a="161599187" X-IronPort-AV: E=Sophos;i="5.81,174,1610438400"; d="scan'208";a="161599187" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2021 10:20:39 -0800 IronPort-SDR: ZGiW8cuzpjKfu6z13MTLeNl7yq4ywVl7V0hg0bGYC70sGF+xoid4yHjnY9Ut4hUJWYK+nNu3/8 Egr94HRZE9ww== X-IronPort-AV: E=Sophos;i="5.81,174,1610438400"; d="scan'208";a="491231837" Received: from sarcot-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.56.203]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2021 10:20:37 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Feb 2021 10:21:59 -0800 Message-Id: <20210212182201.155043-1-jose.souza@intel.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/display/adl_s: Fix dpclka_cfgcr0_clk_off mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The cfgcr0/1_clk_off mapping is wrong for adl-s what could cause the wrong clock being disabled and leaving a not needed clock running consuming more power than needed. Bspec: 50287 Bspec: 53812 Bspec: 53723 Fixes: d6d2bc996e45 ("drm/i915/adl_s: Configure Port clock registers for ADL-S") Cc: Aditya Swarup Cc: Lucas De Marchi Cc: Matt Roper Signed-off-by: José Roberto de Souza Reviewed-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2d6906f6995f..7631e080349d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1585,7 +1585,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, enum phy phy) { - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + return ADLS_DPCLKA_CFGCR_DDI_CLK_OFF(phy); + } else if (IS_ROCKETLAKE(dev_priv)) { return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } else if (intel_phy_is_combo(dev_priv, phy)) { return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 224ad897af34..7c69b50ccc5c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10416,6 +10416,18 @@ enum skl_power_gate { ADLS_DPCLKA_DDIJ_SEL_MASK, \ ADLS_DPCLKA_DDIK_SEL_MASK) +#define _ADLS_DPCLKA_DDIA_CLK_OFF REG_BIT(10) +#define _ADLS_DPCLKA_DDIB_CLK_OFF REG_BIT(11) +#define _ADLS_DPCLKA_DDII_CLK_OFF REG_BIT(24) +#define _ADLS_DPCLKA_DDIJ_CLK_OFF REG_BIT(4) +#define _ADLS_DPCLKA_DDIK_CLK_OFF REG_BIT(5) +#define ADLS_DPCLKA_CFGCR_DDI_CLK_OFF(phy) _PICK((phy), \ + _ADLS_DPCLKA_DDIA_CLK_OFF, \ + _ADLS_DPCLKA_DDIB_CLK_OFF, \ + _ADLS_DPCLKA_DDII_CLK_OFF, \ + _ADLS_DPCLKA_DDIJ_CLK_OFF, \ + _ADLS_DPCLKA_DDIK_CLK_OFF) + /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014