From patchwork Mon Feb 22 11:24:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 12098367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65287C433E0 for ; Mon, 22 Feb 2021 11:23:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 086B760C3D for ; Mon, 22 Feb 2021 11:23:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 086B760C3D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 501DE6E945; Mon, 22 Feb 2021 11:23:07 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4BF3A6E945 for ; Mon, 22 Feb 2021 11:23:06 +0000 (UTC) IronPort-SDR: kf4kXR8qNVU/kiZcAhbFQ5WzQcS3sGFQow2Xa4/+1fptVuu0aN0Uk2vFL6XZ/7omX73ffhUK17 40JsifscWyeg== X-IronPort-AV: E=McAfee;i="6000,8403,9902"; a="245834175" X-IronPort-AV: E=Sophos;i="5.81,197,1610438400"; d="scan'208";a="245834175" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2021 03:23:05 -0800 IronPort-SDR: HGPiHq9bRNOkmRVPWaruF4D6YmWPrAMu3GiRmYQ8HZxyTg5j9P2lUq72M6/GF/HgwgWH55r2OR 2ql6ZS6lJvIw== X-IronPort-AV: E=Sophos;i="5.81,197,1610438400"; d="scan'208";a="498530901" Received: from helsinki.fi.intel.com ([10.237.66.162]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2021 03:23:03 -0800 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Feb 2021 13:24:15 +0200 Message-Id: <20210222112415.1523930-1-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/display: Do not allow DC3CO if PSR SF is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exitmachanism has an issue with using of SelectiveFecth and PSR2 ManualTracking. And as new GEN12+ platform like RKL, ADL-S/P don't have PSR2 HW tracking, Selective Fetch wiil be enabled by default. Therefore if the system enables PSR SelectiveFetch / PSR ManualTracking, it does not allow DC3CO dc state, in that case. When this DC3CO exit issue is addressed while PSR SF is enabled, this restriction should be removed. Cc: José Roberto de Souza Cc: Anshuman Gupta Signed-off-by: Gwan-gyeong Mun --- .../drm/i915/display/intel_display_power.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index f00c1750febd..b385b3f082f2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -804,10 +804,12 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) mask = DC_STATE_EN_UPTO_DC5; - if (INTEL_GEN(dev_priv) >= 12) - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 - | DC_STATE_EN_DC9; - else if (IS_GEN(dev_priv, 11)) + if (INTEL_GEN(dev_priv) >= 12) { + /* DMC's DC3CO exit machanism has an issue with SelectiveFecth */ + if (!dev_priv->params.enable_psr2_sel_fetch) + mask |= DC_STATE_EN_DC3CO; + mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; + } else if (IS_GEN(dev_priv, 11)) mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; else if (IS_GEN9_LP(dev_priv)) mask |= DC_STATE_EN_DC9; @@ -4588,10 +4590,15 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, switch (requested_dc) { case 4: - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; + /* DMC's DC3CO exit machanism has an issue with SelectiveFecth */ + if (!dev_priv->params.enable_psr2_sel_fetch) + mask |= DC_STATE_EN_DC3CO; + mask |= DC_STATE_EN_UPTO_DC6; break; case 3: - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; + if (!dev_priv->params.enable_psr2_sel_fetch) + mask |= DC_STATE_EN_DC3CO; + mask |= DC_STATE_EN_UPTO_DC5; break; case 2: mask |= DC_STATE_EN_UPTO_DC6;