From patchwork Wed Feb 24 15:29:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Piotr_Pi=C3=B3rkowski?= X-Patchwork-Id: 12102049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D76EC433E0 for ; Wed, 24 Feb 2021 15:31:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BDFE564ED3 for ; Wed, 24 Feb 2021 15:31:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BDFE564ED3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D94C6EAD8; Wed, 24 Feb 2021 15:31:58 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id F1D6A6EAD8 for ; Wed, 24 Feb 2021 15:31:56 +0000 (UTC) IronPort-SDR: 35WItwdmamYvNfJ1+M1wJgzjMFpSmY/3J6AWQgTticJ2u0BNu0HHSGQw6cKzD3sWkcdRUPA2g7 OmgSygRiv8Ug== X-IronPort-AV: E=McAfee;i="6000,8403,9904"; a="165066766" X-IronPort-AV: E=Sophos;i="5.81,203,1610438400"; d="scan'208";a="165066766" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2021 07:31:56 -0800 IronPort-SDR: vzPJFfI7WPX4aY+vFclPTrUvBbIvgiPBFNZzQvQrXCJyY9K+trLWFCrn7hBYuBq6ZqOklxGH9R zxLrnE6CmfTA== X-IronPort-AV: E=Sophos;i="5.81,203,1610438400"; d="scan'208";a="403755524" Received: from unknown (HELO localhost) ([172.28.172.35]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2021 07:31:54 -0800 From: "Piorkowski, Piotr" To: intel-gfx@lists.freedesktop.org Date: Wed, 24 Feb 2021 16:29:25 +0100 Message-Id: <20210224152925.1969970-1-piotr.piorkowski@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: Verify dma_addr in gen8_ggtt_pte_encode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michal Winiarski , Matthew Auld Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Piotr Piórkowski Until now, the gen8_ggtt_pte_encode function, responsible for the preparation of GGTT PTE, has not verified in any way whether the address given as the parameter is correct. By adding a GGTT address mask, we can easily verify that dma_addr will not fit in the PTE field. While around, cleanup a place where we hold all GEN12 GGTT PTE masks, and the addition of the PTE description. Bspec: 45015 Signed-off-by: Piotr Piórkowski Cc: Matthew Auld Cc: Michal Wajdeczko Cc: Michal Winiarski --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_gtt.h | 13 ++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index b0b8ded834f0..52b2428da431 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -193,6 +193,8 @@ static u64 gen8_ggtt_pte_encode(dma_addr_t addr, { gen8_pte_t pte = addr | _PAGE_PRESENT; + GEM_BUG_ON(addr & ~GEN12_GGTT_PTE_ADDR_MASK); + if (flags & PTE_LM) pte |= GEN12_GGTT_PTE_LM; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 24b5808df16d..c82bbe307668 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -87,7 +87,18 @@ typedef u64 gen8_pte_t; #define GEN12_PPGTT_PTE_LM BIT_ULL(11) -#define GEN12_GGTT_PTE_LM BIT_ULL(1) +/* + * DOC: GEN12 GGTT Table Entry format + * + * +----------+---------+---------+--------------+---------+ + * | 63:46 | 45:12 | 11:2 | 1 | 0 | + * +==========+=========+=========+==============+=========+ + * | Ignored | Address | Ignored | Local Memory | Present | + * +----------+---------+---------+--------------+---------+ + */ + +#define GEN12_GGTT_PTE_LM BIT_ULL(1) +#define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12) /* * Cacheability Control is a 4-bit value. The low three bits are stored in bits