| Message ID | 20210311182612.17004-1-swathi.dhanavanthri@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Add Wa_14011060649 | expand |
On Thu, Mar 11, 2021 at 10:26:12AM -0800, Swathi Dhanavanthri wrote: > This is a permanent workaround for TGL,RKL,DG1 and ADLS. > > Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 2 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 3b4a7da60f0b..683a0446337a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1117,11 +1117,34 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); > } > > +/* > + * This is a common function for WA 14011060649 > + */ This comment doesn't really add anything useful; the function name itself makes it clear that it applies to WA 14011060649. A more useful thing to comment on here is that although this workaround programs some per-engine registers, those register values persist through engine resets which is why this doesn't get added to a per-engine workaround list; it should only be applied on the GT workaround list. With an updated comment, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > +static void > +wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + struct intel_engine_cs *engine; > + struct intel_gt *gt = &i915->gt; > + int id; > + > + for_each_engine(engine, gt, id) { > + if ((engine->class != VIDEO_DECODE_CLASS) || > + (engine->instance % 2)) > + continue; > + > + wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), > + IECPUNIT_CLKGATE_DIS); > + } > +} > + > static void > gen12_gt_workarounds_init(struct drm_i915_private *i915, > struct i915_wa_list *wal) > { > wa_init_mcr(i915, wal); > + > + /* Wa_14011060649:tgl,rkl,dg1,adls */ > + wa_14011060649(i915, wal); > } > > static void > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e5dd0203991b..cc60556306e2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2715,6 +2715,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ > #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ > > +#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) > +#define IECPUNIT_CLKGATE_DIS REG_BIT(22) > + > #define ERROR_GEN6 _MMIO(0x40a0) > #define GEN7_ERR_INT _MMIO(0x44040) > #define ERR_INT_POISON (1 << 31) > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3b4a7da60f0b..683a0446337a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1117,11 +1117,34 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); } +/* + * This is a common function for WA 14011060649 + */ +static void +wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + struct intel_engine_cs *engine; + struct intel_gt *gt = &i915->gt; + int id; + + for_each_engine(engine, gt, id) { + if ((engine->class != VIDEO_DECODE_CLASS) || + (engine->instance % 2)) + continue; + + wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), + IECPUNIT_CLKGATE_DIS); + } +} + static void gen12_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { wa_init_mcr(i915, wal); + + /* Wa_14011060649:tgl,rkl,dg1,adls */ + wa_14011060649(i915, wal); } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e5dd0203991b..cc60556306e2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2715,6 +2715,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ +#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) +#define IECPUNIT_CLKGATE_DIS REG_BIT(22) + #define ERROR_GEN6 _MMIO(0x40a0) #define GEN7_ERR_INT _MMIO(0x44040) #define ERR_INT_POISON (1 << 31)
This is a permanent workaround for TGL,RKL,DG1 and ADLS. Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 26 insertions(+)