From patchwork Fri Apr 30 21:27:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12234421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80B48C433B4 for ; Fri, 30 Apr 2021 21:25:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0BA2661159 for ; Fri, 30 Apr 2021 21:25:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0BA2661159 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72FCB6F5E1; Fri, 30 Apr 2021 21:25:27 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F7E96F5E1 for ; Fri, 30 Apr 2021 21:25:26 +0000 (UTC) IronPort-SDR: b9opifU4GuNLsoeA1xfZrsMjucUJFBG7rXCCVS0O0h760GMJ3+WBWvvnFmwFGHXzWEMN1J3wam HaWl2wS+EPfg== X-IronPort-AV: E=McAfee;i="6200,9189,9970"; a="261319718" X-IronPort-AV: E=Sophos;i="5.82,263,1613462400"; d="scan'208";a="261319718" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 14:25:19 -0700 IronPort-SDR: XRYe1h5jvueldU1Gqu5Pj+Icv8Gty2cBJgsAsHemDpEjB4dO4en27/Gr3q7Eyq1s6Yh8YcW6B9 eLynkJ7FH/4A== X-IronPort-AV: E=Sophos;i="5.82,263,1613462400"; d="scan'208";a="527788415" Received: from camangan-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.3.74]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 14:25:18 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Apr 2021 14:27:44 -0700 Message-Id: <20210430212744.88171-1-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/display/tgl+: Add new sequence step for MST + FEC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For DP 1.4 sinks + MST + FEC it is required to prevent a FEC stall signaling. BSpec: 49190 BSpec: 54128 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 28 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 9e406d9722c5..e7b636ba6982 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -376,6 +376,30 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, old_crtc_state, old_conn_state); } +static void intel_mst_config_fec(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (DISPLAY_VER(i915) >= 12 && crtc_state->fec_enable && + intel_dp->dpcd[DP_DPCD_REV] == DP_DPCD_REV_14) + intel_de_rmw(i915, CHICKEN_TRANS(crtc_state->cpu_transcoder), + 0, PREVENT_FEC_STALL_SIGNALING); +} + +static void intel_mst_unconfig_fec(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (DISPLAY_VER(i915) >= 12 && crtc_state->fec_enable && + intel_dp->dpcd[DP_DPCD_REV] == DP_DPCD_REV_14) + intel_de_rmw(i915, CHICKEN_TRANS(crtc_state->cpu_transcoder), + PREVENT_FEC_STALL_SIGNALING, 0); +} + static void intel_mst_post_disable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, @@ -400,6 +424,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_disable_pipe(old_crtc_state); + intel_mst_unconfig_fec(encoder, old_crtc_state); + drm_dp_update_payload_part2(&intel_dp->mst_mgr); clear_act_sent(encoder, old_crtc_state); @@ -563,6 +589,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_dp_update_payload_part2(&intel_dp->mst_mgr); + intel_mst_config_fec(encoder, pipe_config); + intel_enable_pipe(pipe_config); intel_crtc_vblank_on(pipe_config); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9ffd173f8b7f..6fe7aebed4f9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8086,6 +8086,7 @@ enum { #define HSW_FRAME_START_DELAY_MASK (3 << 27) #define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ +#define PREVENT_FEC_STALL_SIGNALING BIT(23) #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */