From patchwork Wed May 5 21:38:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12241087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 977D6C433B4 for ; Wed, 5 May 2021 21:35:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C903613BC for ; Wed, 5 May 2021 21:35:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2C903613BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B191E6E483; Wed, 5 May 2021 21:35:12 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FDCE6E483 for ; Wed, 5 May 2021 21:35:11 +0000 (UTC) IronPort-SDR: kgVpmJHyJrrC6b+ODzyMyYMPUZQe7prZ4rc5r4LRiHmqcb1U3k07DJLv4F7OReT7c4nPSXrwoV 4IerP3FGU2Iw== X-IronPort-AV: E=McAfee;i="6200,9189,9975"; a="177869511" X-IronPort-AV: E=Sophos;i="5.82,276,1613462400"; d="scan'208";a="177869511" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2021 14:35:10 -0700 IronPort-SDR: YMqJM3i/uO2N9l5TEcKx2EKlX5F2vMPBZUBVxLTUn5vWA0xQ93t82UR7uTnDpz5F7tWgZJqTPy OwIrCrMasvdQ== X-IronPort-AV: E=Sophos;i="5.82,276,1613462400"; d="scan'208";a="430065594" Received: from srajen2x-mobl5.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.36.128]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2021 14:35:10 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 5 May 2021 14:38:01 -0700 Message-Id: <20210505213801.80772-1-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 sel fetch in TGL pre-production X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The implementation of two workarounds are missing causing failures in CI with pre-production HW. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e3c30dcadcd1..406ba9a712a8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -720,6 +720,13 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, } } + /* Wa_14010254185 Wa_14010103792 */ + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); + return false; + } + return crtc_state->enable_psr2_sel_fetch = true; }