| Message ID | 20210506173049.72503-4-matthew.brost@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | GuC submission / DRM scheduler integration plan + new uAPI | expand |
On Thu, May 06, 2021 at 10:30:47AM -0700, Matthew Brost wrote: > Expose logical engine instance to user via query engine info IOCTL. This > is required for split-frame workloads as these need to be placed on > engines in a logically contiguous order. The logical mapping can change > based on fusing. Rather than having user have knowledge of the fusing we > simply just expose the logical mapping with the existing query engine > info IOCTL. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Tony Ye <tony.ye@intel.com> > CC: Carl Zhang <carl.zhang@intel.com> > Cc: Daniel Vetter <daniel.vetter@intel.com> > Cc: Jason Ekstrand <jason@jlekstrand.net> > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > --- > include/uapi/drm/i915_drm.h | 7 ++++++- Two things on all these 3 patches: - Until we've merged the uapi it shouldn't show up in uapi headers. See what Matt A. has done with a fake local header in Documentation/gpu/rfc which you can pull in. - Since this one is tiny I think just the text in the rfc is good enough, I'd drop this. - Squash the others in with the parallel submit rfc patch so that the structs and long-form text are all in one patch please, makes reviewing the overall thing a bit simpler. Rule is to have a complete change per patch, and then not split things further. > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index 9f331ad629f5..26d2e135aa31 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -2396,14 +2396,19 @@ struct drm_i915_engine_info { > > /** @flags: Engine flags. */ > __u64 flags; > +#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) > > /** @capabilities: Capabilities of this engine. */ > __u64 capabilities; > #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) > #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) > > + /** Logical engine instance */ I think in the final version that we merge with the uapi this should: - explain why we need this - link to relevant other uapi like the paralle submit extension Cheers, Daniel > + __u16 logical_instance; > + > /** @rsvd1: Reserved fields. */ > - __u64 rsvd1[4]; > + __u16 rsvd1[3]; > + __u64 rsvd2[3]; > }; > > /** > -- > 2.28.0 >
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 9f331ad629f5..26d2e135aa31 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2396,14 +2396,19 @@ struct drm_i915_engine_info { /** @flags: Engine flags. */ __u64 flags; +#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) /** @capabilities: Capabilities of this engine. */ __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) + /** Logical engine instance */ + __u16 logical_instance; + /** @rsvd1: Reserved fields. */ - __u64 rsvd1[4]; + __u16 rsvd1[3]; + __u64 rsvd2[3]; }; /**
Expose logical engine instance to user via query engine info IOCTL. This is required for split-frame workloads as these need to be placed on engines in a logically contiguous order. The logical mapping can change based on fusing. Rather than having user have knowledge of the fusing we simply just expose the logical mapping with the existing query engine info IOCTL. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Tony Ye <tony.ye@intel.com> CC: Carl Zhang <carl.zhang@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- include/uapi/drm/i915_drm.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)