From patchwork Fri May 14 05:28:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12257139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4527C43460 for ; Fri, 14 May 2021 05:25:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F3D661028 for ; Fri, 14 May 2021 05:25:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8F3D661028 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E2006EE0A; Fri, 14 May 2021 05:25:50 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C18198970B for ; Fri, 14 May 2021 05:25:45 +0000 (UTC) IronPort-SDR: 4Wv6gHbOqEAzyhhstnVB5MYo3I8dempOEXGHu1FHbo4ellHYa4gPiMMYiy3RhNZp+8K9hJDzgN F86Uen34oOug== X-IronPort-AV: E=McAfee;i="6200,9189,9983"; a="179714752" X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="179714752" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 IronPort-SDR: SnwgUKwvuGnaxKZ5Y16txcHdm40acirYKskORmnVsij2eOTB4KA9G1DsJjlKSkz9TOd7kNu5SO oyQGRsx5rLRg== X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="626679115" Received: from thoang1-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.1.122]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 13 May 2021 22:28:42 -0700 Message-Id: <20210514052843.9456-3-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210514052843.9456-1-jose.souza@intel.com> References: <20210514052843.9456-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: Replace intel_dp_set_infoframes() enable calls by dig_port->set_infoframes() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" intel_dp_set_infoframes() and set_infoframes() hook had some code overlapping that makes sense us try to drop it. set_infoframes() is called during the pre_enable phase while intel_dp_set_infoframes() was being called in the enable phase but it was only enabling DP_SDP_VSC and HDMI_PACKET_TYPE_GAMUT_METADATA infoframes, that were added back to hsw_set_infoframes() and lspcon_set_infoframes(). Did not found any information about why this difference of phase but if it is not supported our CI will probably catch it. As hsw_set_infoframes() will now be called during the fastset updates the assert_hdmi_transcoder_func_disabled() check needed to be dropped. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++----- drivers/gpu/drm/i915/display/intel_dp.c | 36 ++------------------- drivers/gpu/drm/i915/display/intel_dp.h | 6 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 ++++------- drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++ 5 files changed, 17 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ba2f98881638..04cf7815da2f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2762,9 +2762,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, conn_state); /* FIXME precompute everything properly */ - if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) - dig_port->set_infoframes(encoder, true, crtc_state, - conn_state); + dig_port->set_infoframes(encoder, true, crtc_state, conn_state); } } @@ -3033,7 +3031,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum port port = encoder->port; if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) @@ -3042,9 +3039,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, intel_edp_backlight_on(crtc_state, conn_state); intel_psr_enable(intel_dp, crtc_state, conn_state); - if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); - intel_edp_drrs_enable(intel_dp, crtc_state); if (crtc_state->has_audio) @@ -3245,12 +3239,13 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state, conn_state); - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + dig_port->set_infoframes(encoder, true, crtc_state, conn_state); intel_edp_drrs_update(intel_dp, crtc_state); intel_panel_update_backlight(state, encoder, crtc_state, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 861409bc210d..270d9d7ac614 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2757,9 +2757,9 @@ intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_in return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; } -static void intel_write_dp_sdp(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type) +void intel_write_dp_sdp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type) { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -2808,36 +2808,6 @@ void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, &sdp, len); } -void intel_dp_set_infoframes(struct intel_encoder *encoder, - bool enable, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); - u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | - VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | - VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; - u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; - - /* TODO: Add DSC case (DIP_ENABLE_PPS) */ - /* When PSR is enabled, this routine doesn't disable VSC DIP */ - if (!crtc_state->has_psr) - val &= ~VIDEO_DIP_ENABLE_VSC_HSW; - - intel_de_write(dev_priv, reg, val); - intel_de_posting_read(dev_priv, reg); - - if (!enable) - return; - - /* When PSR is enabled, VSC SDP is handled by PSR routine */ - if (!crtc_state->has_psr) - intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); - - intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); -} - static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, const void *buffer, size_t size) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 680631b5b437..be5ad619d573 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -99,9 +99,9 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, struct drm_dp_vsc_sdp *vsc); -void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state); +void intel_write_dp_sdp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type); void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 4b970587067d..fd656370053b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -71,16 +71,6 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) "HDMI port enabled, expecting disabled\n"); } -static void -assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, - enum transcoder cpu_transcoder) -{ - drm_WARN(&dev_priv->drm, - intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & - TRANS_DDI_FUNC_ENABLE, - "HDMI transcoder function enabled, expecting disabled\n"); -} - static u32 g4x_infoframe_index(unsigned int type) { switch (type) { @@ -1209,9 +1199,6 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); u32 val = intel_de_read(dev_priv, reg); - assert_hdmi_transcoder_func_disabled(dev_priv, - crtc_state->cpu_transcoder); - val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | @@ -1241,6 +1228,12 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_DRM, &crtc_state->infoframes.drm); + + /* When PSR is enabled, VSC SDP is handled by PSR routine */ + if (!crtc_state->has_psr) + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); + + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); } void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 05d2d750fa53..e4105156822b 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -565,6 +565,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, buf, ret); + + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); } static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)