From patchwork Fri May 14 23:22:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12259267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AC03C433ED for ; Fri, 14 May 2021 23:19:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B4F1F611CE for ; Fri, 14 May 2021 23:19:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B4F1F611CE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36E7D6F4B0; Fri, 14 May 2021 23:19:45 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7D9146F4B0 for ; Fri, 14 May 2021 23:19:44 +0000 (UTC) IronPort-SDR: W/QyLXXW8SuYDKBV8FMKALXEqKgqwZKInFSa//DMpaw6UadRbM0OFWd7MNJs/aQxzzsCw7KtQD 6FRMCSAirB+w== X-IronPort-AV: E=McAfee;i="6200,9189,9984"; a="199938030" X-IronPort-AV: E=Sophos;i="5.82,300,1613462400"; d="scan'208";a="199938030" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2021 16:19:43 -0700 IronPort-SDR: mTj0sVSny+id9SiMgXtwhcAN5BbrYs9zVnNo+cz1VkT3knaSpo3ajXXr15auksoR49crjHd3ZK KBimoqmrZLVQ== X-IronPort-AV: E=Sophos;i="5.82,300,1613462400"; d="scan'208";a="627453929" Received: from rmjoslin-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.1.40]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2021 16:19:41 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 14 May 2021 16:22:44 -0700 Message-Id: <20210514232247.144542-1-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") is not allowing fastsets to happen when PSR states changes but PSR is a feature that can be enabled and disabled during fastsets. So here moving the PSR pipe conf checks to a block that is only executed when checking if HW state matches with requested state, not during the phase where it checks if fastset is possible or not. There still a state mismatch not allowing fastsets between states turning off or on PSR because of crtc_state->infoframes.enable BIT(DP_SDP_VSC) but at least for now it will allow a fastset between PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not work with PSR2, but the remaning issue will be fixed in a future patch. Cc: Gwan-gyeong Mun Cc: Radhakrishna Sripada Reported-by: Ville Syrjälä Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0c2b194006f8..51f499271cc8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8548,6 +8548,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); if (bp_gamma) PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); + + PIPE_CONF_CHECK_BOOL(has_psr); + PIPE_CONF_CHECK_BOOL(has_psr2); + PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); + PIPE_CONF_CHECK_I(dc3co_exitline); } PIPE_CONF_CHECK_BOOL(double_wide); @@ -8631,11 +8636,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.flipline); PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_psr2); - PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); - PIPE_CONF_CHECK_I(dc3co_exitline); - #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_BOOL