diff mbox series

[2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer

Message ID 20210625235600.765677-2-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915/display/adl_p: Implement PSR changes | expand

Commit Message

Souza, Jose June 25, 2021, 11:56 p.m. UTC 
This is now a requirement for all display 12 and newer, not only for
tigerlake.

BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Lucas De Marchi July 20, 2021, 7:51 p.m. UTC | #1 
On Fri, Jun 25, 2021 at 04:56:00PM -0700, Jose Souza wrote:
>This is now a requirement for all display 12 and newer, not only for
>tigerlake.
>
>BSpec: 50422
>Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>index 7dc72e4a4656b..270b1f26566df 100644
>--- a/drivers/gpu/drm/i915/display/intel_fbc.c
>+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>@@ -911,11 +911,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> 	}
>
> 	/*
>-	 * Tigerlake is not supporting FBC with PSR2.
>+	 * Display 12+ is not supporting FBC with PSR2.
> 	 * Recommendation is to keep this combination disabled
> 	 * Bspec: 50422 HSD: 14010260002
> 	 */
>-	if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
>+	if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) {
> 		fbc->no_fbc_reason = "not supported with PSR2";
> 		return false;
> 	}
>-- 
>2.32.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7dc72e4a4656b..270b1f26566df 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -911,11 +911,11 @@  static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 	}
 
 	/*
-	 * Tigerlake is not supporting FBC with PSR2.
+	 * Display 12+ is not supporting FBC with PSR2.
 	 * Recommendation is to keep this combination disabled
 	 * Bspec: 50422 HSD: 14010260002
 	 */
-	if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
+	if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) {
 		fbc->no_fbc_reason = "not supported with PSR2";
 		return false;
 	}