[V3] drm/i915/adl_s: Fix dma_mask_size to 39 bit

Commit Message

Tejas Upadhyay July 8, 2021, 7:12 a.m. UTC

46 bit addressing enables you to use 4 bits  to support some
MKTME features, and 3 more bits for Optane support that uses
a subset of MTKME for persistent memory.

But GTT addressing sticking to 39 bit addressing, thus setting
dma_mask_size to 39 fixes below tests :
igt@i915_selftest@live@mman
igt@kms_big_fb@linear-32bpp-rotate-0
igt@gem_create@create-clear
igt@gem_mmap_offset@clear
igt@gem_mmap_gtt@cpuset-big-copy

In a way solves Gitlab#3142
https://gitlab.freedesktop.org/drm/intel/-/issues/3142, which had
following errors :
DMAR: DRHD: handling fault status reg 2
DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr
7effff9000 [fault reason 05] PTE Write access is not set

0x7effff9000 is suspiciously exactly 39 bits, so it seems likely that
the HW just ends up masking off those extra bits hence DMA errors.

Changes since V2 :
	- dim checkpatch error solved
Changes since V1 :
	- Added more details to commit message - Matthew Auld

Signed-off-by: Tejas Upadhyay <[e-mail]>
Acked-by: Matthew Auld <[e-mail]>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Matthew Auld July 8, 2021, 9:16 a.m. UTC | #1

On Thu, 8 Jul 2021 at 08:21, Tejas Upadhyay
<[e-mail]> wrote:
>
> 46 bit addressing enables you to use 4 bits  to support some
> MKTME features, and 3 more bits for Optane support that uses
> a subset of MTKME for persistent memory.
>
> But GTT addressing sticking to 39 bit addressing, thus setting
> dma_mask_size to 39 fixes below tests :
> igt@i915_selftest@live@mman
> igt@kms_big_fb@linear-32bpp-rotate-0
> igt@gem_create@create-clear
> igt@gem_mmap_offset@clear
> igt@gem_mmap_gtt@cpuset-big-copy
>
> In a way solves Gitlab#3142
> https://gitlab.freedesktop.org/drm/intel/-/issues/3142, which had
> following errors :
> DMAR: DRHD: handling fault status reg 2
> DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr
> 7effff9000 [fault reason 05] PTE Write access is not set
>
> 0x7effff9000 is suspiciously exactly 39 bits, so it seems likely that
> the HW just ends up masking off those extra bits hence DMA errors.
>
> Changes since V2 :
>         - dim checkpatch error solved
> Changes since V1 :
>         - Added more details to commit message - Matthew Auld
>
> Signed-off-by: Tejas Upadhyay <[e-mail]>
> Acked-by: Matthew Auld <[e-mail]>

Pushed to drm-intel-gt-next. Thanks for the patch.

Patch

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a7bfdd827bc8..0fea4c0c6d48 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -934,7 +934,7 @@  static const struct intel_device_info adl_s_info = {
 	.display.has_psr_hw_tracking = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
-	.dma_mask_size = 46,
+	.dma_mask_size = 39,
 };
 
 #define XE_LPD_CURSOR_OFFSETS \