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[4/7] drm/i915: Limit maximum number of memory channels

Message ID 20210708211827.288601-4-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/7] drm/i915: Settle on "adl-x" in WA comments | expand

Commit Message

Souza, Jose July 8, 2021, 9:18 p.m. UTC 
Alderlake-P PCODE is returning 4 memory channels while it has a
maximum of 2.
So adding this limit and printing a debug message but the real fix
will need to come from PCODE.

HSDES: 22013272110
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_dram.c | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 879b0f007be31..de1d426627ef1 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -467,6 +467,10 @@  static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
 	}
 
 	dram_info->num_channels = (val & 0xf0) >> 4;
+	if (dram_info->num_channels > 2) {
+		drm_info(&dev_priv->drm, "More DRAM channels than expected, setting to max.\n");
+		dram_info->num_channels = 2;
+	}
 	dram_info->num_qgv_points = (val & 0xf00) >> 8;
 
 	return 0;