From patchwork Thu Jul 8 23:18:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12366319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0FDCC07E96 for ; Thu, 8 Jul 2021 23:18:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB4CC613E1 for ; Thu, 8 Jul 2021 23:18:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AB4CC613E1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6175B6E93B; Thu, 8 Jul 2021 23:18:29 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9DFDA6E934 for ; Thu, 8 Jul 2021 23:18:26 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10039"; a="209578459" X-IronPort-AV: E=Sophos;i="5.84,225,1620716400"; d="scan'208";a="209578459" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2021 16:18:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,225,1620716400"; d="scan'208";a="482707914" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by fmsmga004.fm.intel.com with ESMTP; 08 Jul 2021 16:18:24 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Jul 2021 16:18:15 -0700 Message-Id: <20210708231821.9163-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210708231821.9163-1-anusha.srivatsa@intel.com> References: <20210708231821.9163-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/10] drm/i915/jsl_ehl: Use revid->stepping tables X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Switch JSL/EHL to use a revid->stepping table as we're trying to do on all platforms going forward. Bspec: 29153 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 9 ++++----- drivers/gpu/drm/i915/intel_step.c | 8 ++++++++ 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 882bfd499e55..dfc31b682848 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2674,7 +2674,7 @@ static bool ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) { return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && - IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) || + IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) && i915->dpll.ref_clks.nssc == 38400; } diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e2d8acb8c1c9..4c0c15bbdac2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) /* Wa_1607087056:icl,ehl,jsl */ if (IS_ICELAKE(i915) || - IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) + IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0)) wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e26ff8624945..78db92bbb1c6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1519,11 +1519,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ICL_GT_STEP(p, since, until) \ (IS_ICELAKE(p) && IS_GT_STEP(p, since, until)) -#define EHL_REVID_A0 0x0 -#define EHL_REVID_B0 0x1 - -#define IS_JSL_EHL_REVID(p, since, until) \ - (IS_JSL_EHL(p) && IS_REVID(p, since, until)) +#define IS_JSL_EHL_GT_STEP(p, since, until) \ + (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until)) +#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \ + (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until)) #define IS_TGL_DISPLAY_STEP(__i915, since, until) \ (IS_TIGERLAKE(__i915) && \ diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 4d8248cf67d3..61666a3dd672 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -51,6 +51,11 @@ static const struct intel_step_info icl_revid_step_tbl[] = { [7] = { .gt_step = STEP_D0, .display_step = STEP_D0 }, }; +static const struct intel_step_info jsl_ehl_revid_step_tbl[] = { + [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, + [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, +}; + static const struct intel_step_info tgl_uy_revid_step_tbl[] = { [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -98,6 +103,9 @@ void intel_step_init(struct drm_i915_private *i915) } else if (IS_TIGERLAKE(i915)) { revids = tgl_revid_step_tbl; size = ARRAY_SIZE(tgl_revid_step_tbl); + } else if (IS_JSL_EHL(i915)) { + revids = jsl_ehl_revid_step_tbl; + size = ARRAY_SIZE(jsl_ehl_revid_step_tbl); } else if (IS_ICELAKE(i915)) { revids = icl_revid_step_tbl; size = ARRAY_SIZE(icl_revid_step_tbl);