@@ -2159,6 +2159,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
+ /*
+ * VDSC engine can process only 1 pixel per Cd clock.
+ * In case VDSC is used and max slice count == 1,
+ * max supported pixel clock should be 100% of CD clock.
+ * Then do min_cdclk and pixel clock comparison to get cdclk.
+ */
+ if (crtc_state->dsc.compression_enable &&
+ crtc_state->dsc.slice_count == 1)
+ min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
/*
* HACK. Currently for TGL platforms we calculate
* min_cdclk initially based on pixel_rate divided
VDSC engine can process only 1 pixel per Cd clock. In case VDSC is used and max slice count == 1, max supported pixel clock should be 100% of CD clock. Then do min_cdclk and pixel clock comparison to get proper min cdclk. v2: - Check for dsc enable and slice count ==1 then allow to double confirm min cdclk value. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: William Tseng <william.tseng@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++ 1 file changed, 10 insertions(+)