From patchwork Tue Aug 3 20:13:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 12417291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7ABCC4320A for ; Tue, 3 Aug 2021 20:13:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 847BB60F45 for ; Tue, 3 Aug 2021 20:13:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 847BB60F45 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 235EB6E8C1; Tue, 3 Aug 2021 20:13:53 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 302DE6E8BE; Tue, 3 Aug 2021 20:13:51 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10065"; a="213499168" X-IronPort-AV: E=Sophos;i="5.84,292,1620716400"; d="scan'208";a="213499168" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 13:13:50 -0700 X-IronPort-AV: E=Sophos;i="5.84,292,1620716400"; d="scan'208";a="568776533" Received: from unerlige-ril-10.jf.intel.com ([10.165.21.208]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 13:13:50 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org, Lionel G Landwerlin , Ashutosh Dixit , daniel@ffwll.ch Cc: dri-devel@lists.freedesktop.org Date: Tue, 3 Aug 2021 13:13:42 -0700 Message-Id: <20210803201349.31031-2-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210803201349.31031-1-umesh.nerlige.ramappa@intel.com> References: <20210803201349.31031-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/8] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Refactor intel_engine_apply_whitelist into locked and unlocked versions so that a caller who already has the lock can apply whitelist. v2: Fix sparse warning v3: (Chris) - Drop prefix and suffix for static function - Use longest to shortest line ordering for variable declaration Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 46 ++++++++++++++------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 053fa7251cd0..011cde0bc38d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1108,7 +1108,8 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915) } static enum forcewake_domains -wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) +wal_get_fw(struct intel_uncore *uncore, const struct i915_wa_list *wal, + unsigned int op) { enum forcewake_domains fw = 0; struct i915_wa *wa; @@ -1117,8 +1118,7 @@ wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) for (i = 0, wa = wal->list; i < wal->count; i++, wa++) fw |= intel_uncore_forcewake_for_reg(uncore, wa->reg, - FW_REG_READ | - FW_REG_WRITE); + op); return fw; } @@ -1149,7 +1149,7 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) if (!wal->count) return; - fw = wal_get_fw_for_rmw(uncore, wal); + fw = wal_get_fw(uncore, wal, FW_REG_READ | FW_REG_WRITE); spin_lock_irqsave(&uncore->lock, flags); intel_uncore_forcewake_get__locked(uncore, fw); @@ -1188,7 +1188,7 @@ static bool wa_list_verify(struct intel_gt *gt, unsigned int i; bool ok = true; - fw = wal_get_fw_for_rmw(uncore, wal); + fw = wal_get_fw(uncore, wal, FW_REG_READ | FW_REG_WRITE); spin_lock_irqsave(&uncore->lock, flags); intel_uncore_forcewake_get__locked(uncore, fw); @@ -1477,27 +1477,45 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) wa_init_finish(w); } -void intel_engine_apply_whitelist(struct intel_engine_cs *engine) +static void __engine_apply_whitelist(struct intel_engine_cs *engine) { const struct i915_wa_list *wal = &engine->whitelist; struct intel_uncore *uncore = engine->uncore; const u32 base = engine->mmio_base; + enum forcewake_domains fw; struct i915_wa *wa; unsigned int i; - if (!wal->count) - return; + lockdep_assert_held(&uncore->lock); + + fw = wal_get_fw(uncore, wal, FW_REG_WRITE); + intel_uncore_forcewake_get__locked(uncore, fw); for (i = 0, wa = wal->list; i < wal->count; i++, wa++) - intel_uncore_write(uncore, - RING_FORCE_TO_NONPRIV(base, i), - i915_mmio_reg_offset(wa->reg)); + intel_uncore_write_fw(uncore, + RING_FORCE_TO_NONPRIV(base, i), + i915_mmio_reg_offset(wa->reg)); /* And clear the rest just in case of garbage */ for (; i < RING_MAX_NONPRIV_SLOTS; i++) - intel_uncore_write(uncore, - RING_FORCE_TO_NONPRIV(base, i), - i915_mmio_reg_offset(RING_NOPID(base))); + intel_uncore_write_fw(uncore, + RING_FORCE_TO_NONPRIV(base, i), + i915_mmio_reg_offset(RING_NOPID(base))); + + intel_uncore_forcewake_put__locked(uncore, fw); +} + +void intel_engine_apply_whitelist(struct intel_engine_cs *engine) +{ + const struct i915_wa_list *wal = &engine->whitelist; + unsigned long flags; + + if (!wal->count) + return; + + spin_lock_irqsave(&engine->uncore->lock, flags); + __engine_apply_whitelist(engine); + spin_unlock_irqrestore(&engine->uncore->lock, flags); } static void