| Message ID | 20210820224446.30620-10-matthew.brost@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Parallel submission aka multi-bb execbuf | expand |
On 8/20/2021 15:44, Matthew Brost wrote: > Expose logical engine instance to user via query engine info IOCTL. This > is required for split-frame workloads as these needs to be placed on > engines in a logically contiguous order. The logical mapping can change > based on fusing. Rather than having user have knowledge of the fusing we > simply just expose the logical mapping with the existing query engine > info IOCTL. > > IGT: https://patchwork.freedesktop.org/patch/445637/?series=92854&rev=1 > media UMD: link coming soon > > v2: > (Daniel Vetter) > - Add IGT link, placeholder for media UMD > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > --- > drivers/gpu/drm/i915/i915_query.c | 2 ++ > include/uapi/drm/i915_drm.h | 8 +++++++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c > index e49da36c62fb..8a72923fbdba 100644 > --- a/drivers/gpu/drm/i915/i915_query.c > +++ b/drivers/gpu/drm/i915/i915_query.c > @@ -124,7 +124,9 @@ query_engine_info(struct drm_i915_private *i915, > for_each_uabi_engine(engine, i915) { > info.engine.engine_class = engine->uabi_class; > info.engine.engine_instance = engine->uabi_instance; > + info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE; > info.capabilities = engine->uabi_capabilities; > + info.logical_instance = ilog2(engine->logical_mask); > > if (copy_to_user(info_ptr, &info, sizeof(info))) > return -EFAULT; > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index bde5860b3686..b1248a67b4f8 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -2726,14 +2726,20 @@ struct drm_i915_engine_info { > > /** @flags: Engine flags. */ > __u64 flags; > +#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) > > /** @capabilities: Capabilities of this engine. */ > __u64 capabilities; > #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) > #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) > > + /** @logical_instance: Logical instance of engine */ > + __u16 logical_instance; > + > /** @rsvd1: Reserved fields. */ > - __u64 rsvd1[4]; > + __u16 rsvd1[3]; > + /** @rsvd2: Reserved fields. */ > + __u64 rsvd2[3]; > }; > > /** Any idea why the padding? Would be useful if the comment said 'this structure must be at least/exactly X bytes in size / a multiple of X bytes in size because ...' or whatever. However, not really anything to do with this patch as such, so either way: Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
On Mon, Sep 13, 2021 at 04:06:33PM -0700, John Harrison wrote: > On 8/20/2021 15:44, Matthew Brost wrote: > > Expose logical engine instance to user via query engine info IOCTL. This > > is required for split-frame workloads as these needs to be placed on > > engines in a logically contiguous order. The logical mapping can change > > based on fusing. Rather than having user have knowledge of the fusing we > > simply just expose the logical mapping with the existing query engine > > info IOCTL. > > > > IGT: https://patchwork.freedesktop.org/patch/445637/?series=92854&rev=1 > > media UMD: link coming soon > > > > v2: > > (Daniel Vetter) > > - Add IGT link, placeholder for media UMD > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > --- > > drivers/gpu/drm/i915/i915_query.c | 2 ++ > > include/uapi/drm/i915_drm.h | 8 +++++++- > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c > > index e49da36c62fb..8a72923fbdba 100644 > > --- a/drivers/gpu/drm/i915/i915_query.c > > +++ b/drivers/gpu/drm/i915/i915_query.c > > @@ -124,7 +124,9 @@ query_engine_info(struct drm_i915_private *i915, > > for_each_uabi_engine(engine, i915) { > > info.engine.engine_class = engine->uabi_class; > > info.engine.engine_instance = engine->uabi_instance; > > + info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE; > > info.capabilities = engine->uabi_capabilities; > > + info.logical_instance = ilog2(engine->logical_mask); > > if (copy_to_user(info_ptr, &info, sizeof(info))) > > return -EFAULT; > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > index bde5860b3686..b1248a67b4f8 100644 > > --- a/include/uapi/drm/i915_drm.h > > +++ b/include/uapi/drm/i915_drm.h > > @@ -2726,14 +2726,20 @@ struct drm_i915_engine_info { > > /** @flags: Engine flags. */ > > __u64 flags; > > +#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) > > /** @capabilities: Capabilities of this engine. */ > > __u64 capabilities; > > #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) > > #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) > > + /** @logical_instance: Logical instance of engine */ > > + __u16 logical_instance; > > + > > /** @rsvd1: Reserved fields. */ > > - __u64 rsvd1[4]; > > + __u16 rsvd1[3]; > > + /** @rsvd2: Reserved fields. */ > > + __u64 rsvd2[3]; > > }; > > /** > Any idea why the padding? Would be useful if the comment said 'this > structure must be at least/exactly X bytes in size / a multiple of X bytes > in size because ...' or whatever. > I think this is pretty standard in UABI interface - add a bunch of padding bits in case you need them in the future (i.e. this patch is an example of that). Matt > However, not really anything to do with this patch as such, so either way: > Reviewed-by: John Harrison <John.C.Harrison@Intel.com> >
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index e49da36c62fb..8a72923fbdba 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -124,7 +124,9 @@ query_engine_info(struct drm_i915_private *i915, for_each_uabi_engine(engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; + info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE; info.capabilities = engine->uabi_capabilities; + info.logical_instance = ilog2(engine->logical_mask); if (copy_to_user(info_ptr, &info, sizeof(info))) return -EFAULT; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index bde5860b3686..b1248a67b4f8 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2726,14 +2726,20 @@ struct drm_i915_engine_info { /** @flags: Engine flags. */ __u64 flags; +#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) /** @capabilities: Capabilities of this engine. */ __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) + /** @logical_instance: Logical instance of engine */ + __u16 logical_instance; + /** @rsvd1: Reserved fields. */ - __u64 rsvd1[4]; + __u16 rsvd1[3]; + /** @rsvd2: Reserved fields. */ + __u64 rsvd2[3]; }; /**
Expose logical engine instance to user via query engine info IOCTL. This is required for split-frame workloads as these needs to be placed on engines in a logically contiguous order. The logical mapping can change based on fusing. Rather than having user have knowledge of the fusing we simply just expose the logical mapping with the existing query engine info IOCTL. IGT: https://patchwork.freedesktop.org/patch/445637/?series=92854&rev=1 media UMD: link coming soon v2: (Daniel Vetter) - Add IGT link, placeholder for media UMD Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/i915_query.c | 2 ++ include/uapi/drm/i915_drm.h | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-)