From patchwork Wed Aug 25 00:58:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12456147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FA59C4320A for ; Wed, 25 Aug 2021 00:53:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B60C61176 for ; Wed, 25 Aug 2021 00:53:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0B60C61176 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97A7C6E0F4; Wed, 25 Aug 2021 00:53:58 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4CAF7896FA for ; Wed, 25 Aug 2021 00:53:43 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10086"; a="204623095" X-IronPort-AV: E=Sophos;i="5.84,349,1620716400"; d="scan'208";a="204623095" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2021 17:53:42 -0700 X-IronPort-AV: E=Sophos;i="5.84,349,1620716400"; d="scan'208";a="507826417" Received: from josouza-mobl2.jf.intel.com (HELO josouza-mobl2.intel.com) ([10.24.14.60]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2021 17:53:42 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= Date: Tue, 24 Aug 2021 17:58:38 -0700 Message-Id: <20210825005840.170796-7-jose.souza@intel.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210825005840.170796-1-jose.souza@intel.com> References: <20210825005840.170796-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 6/8] drm/i915/display: Prepare DRRS for frontbuffer rendering drop X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Frontbuffer rendering will be dropped for modern platforms but before that we to prepare DRRS for it. intel_drrs_flush and intel_drrs_invalidate will not be called for platforms that will not support frontbuffer rendering so DRRS needs another way to be notified about to page flips so it can change between high and low refresh rates as needed. Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 2 ++ drivers/gpu/drm/i915/display/intel_drrs.c | 9 +++++++++ drivers/gpu/drm/i915/display/intel_drrs.h | 4 ++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 794690c0dba56..808002aa439e2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -52,6 +52,7 @@ #include "display/intel_dp_mst.h" #include "display/intel_dpll.h" #include "display/intel_dpll_mgr.h" +#include "display/intel_drrs.h" #include "display/intel_dsi.h" #include "display/intel_dvo.h" #include "display/intel_fb.h" @@ -2436,6 +2437,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state, hsw_enable_ips(new_crtc_state); intel_fbc_post_update(state, crtc); + intel_drrs_page_flip(state, crtc); if (needs_nv12_wa(old_crtc_state) && !needs_nv12_wa(new_crtc_state)) diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 8583da4e82434..6ae778c306006 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -391,6 +391,15 @@ void intel_drrs_flush(struct drm_i915_private *dev_priv, intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); } +void intel_drrs_page_flip(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); + + intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); +} + /** * intel_drrs_init - Init basic DRRS work and mutex. * @connector: eDP connector diff --git a/drivers/gpu/drm/i915/display/intel_drrs.h b/drivers/gpu/drm/i915/display/intel_drrs.h index 73be7e9a43691..9ec9c447211af 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.h +++ b/drivers/gpu/drm/i915/display/intel_drrs.h @@ -9,6 +9,8 @@ #include struct drm_i915_private; +struct intel_atomic_state; +struct intel_crtc; struct intel_crtc_state; struct intel_connector; struct intel_dp; @@ -23,6 +25,8 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits); void intel_drrs_flush(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits); +void intel_drrs_page_flip(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_drrs_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, int output_bpp, bool constant_n);