[03/10] drm/i915: move more pll/clocks into display struct.

Message ID	20210906034356.2946530-4-airlied@gmail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=0xFZ=N4=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 714CC60ED8 From: Dave Airlie <airlied@gmail.com> To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com> Date: Mon, 6 Sep 2021 13:43:49 +1000 Message-Id: <20210906034356.2946530-4-airlied@gmail.com> In-Reply-To: <20210906034356.2946530-1-airlied@gmail.com> References: <20210906034356.2946530-1-airlied@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="US-ASCII" Subject: [Intel-gfx] [PATCH 03/10] drm/i915: move more pll/clocks into display struct. Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	refactor display structs a little bit \| expand [RFC,00/10] refactor display structs a little bit [01/10] drm/i915: move display funcs into a display struct. [02/10] drm/i915/display: move cdclk info into display [03/10] drm/i915: move more pll/clocks into display struct. [04/10] drm/i915/display: move gmbus into display struct [05/10] drm/i915/display: move intel_dmc into display struct [06/10] drm/i915/display: move mipi_mmio_base to display struct [07/10] drm/i915/display: move pps_mmio_base to display struct [08/10] drm/i915/drrs: just use some local vars to simplify drrs code [09/10] drm/i915/display: move drrs into display struct [10/10] drm/i915/display: move fbc into display struct

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index cb54a0c8b4e0..e52f97c3ecab 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -434,7 +434,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv, static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) { - int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? + int freq_320 = (dev_priv->display.hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; /* @@ -467,7 +467,7 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) * hardware has shown that we just need to write the desired * CCK divider into the Punit register. */ - return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; + return DIV_ROUND_CLOSEST(dev_priv->display.hpll_freq << 1, cdclk) - 1; } } @@ -506,7 +506,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) else default_credits = PFI_CREDIT(8); - if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { + if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->display.czclk_freq) { /* CHV suggested value is 31 or 63 */ if (IS_CHERRYVIEW(dev_priv)) credits = PFI_CREDIT_63; @@ -581,7 +581,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, if (cdclk == 400000) { u32 divider; - divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, + divider = DIV_ROUND_CLOSEST(dev_priv->display.hpll_freq << 1, cdclk) - 1; /* adjust cdclk divider */ @@ -942,9 +942,9 @@ static int skl_cdclk_decimal(int cdclk) static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) { - bool changed = dev_priv->skl_preferred_vco_freq != vco; + bool changed = dev_priv->display.skl_preferred_vco_freq != vco; - dev_priv->skl_preferred_vco_freq = vco; + dev_priv->display.skl_preferred_vco_freq = vco; if (changed) intel_update_max_cdclk(dev_priv); @@ -1151,7 +1151,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) * Use the current vco as our initial * guess as to what the preferred vco is. */ - if (dev_priv->skl_preferred_vco_freq == 0) + if (dev_priv->display.skl_preferred_vco_freq == 0) skl_set_preferred_cdclk_vco(dev_priv, dev_priv->display.cdclk.hw.vco); return; @@ -1159,7 +1159,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) cdclk_config = dev_priv->display.cdclk.hw; - cdclk_config.vco = dev_priv->skl_preferred_vco_freq; + cdclk_config.vco = dev_priv->display.skl_preferred_vco_freq; if (cdclk_config.vco == 0) cdclk_config.vco = 8100000; cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); @@ -2331,7 +2331,7 @@ static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) vco = cdclk_state->logical.vco; if (!vco) - vco = dev_priv->skl_preferred_vco_freq; + vco = dev_priv->display.skl_preferred_vco_freq; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { if (!crtc_state->hw.enable) @@ -2636,7 +2636,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; int max_cdclk, vco; - vco = dev_priv->skl_preferred_vco_freq; + vco = dev_priv->display.skl_preferred_vco_freq; drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); /* @@ -2678,13 +2678,13 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) dev_priv->display.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; } - dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); + dev_priv->display.max_dotclk_freq = intel_compute_max_dotclk(dev_priv); drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", dev_priv->display.max_cdclk_freq); drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", - dev_priv->max_dotclk_freq); + dev_priv->display.max_dotclk_freq); } /** diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 408f82b0dc7d..466ce68ae5e0 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -342,7 +342,7 @@ intel_crt_mode_valid(struct drm_connector *connector, { struct drm_device *dev = connector->dev; struct drm_i915_private *dev_priv = to_i915(dev); - int max_dotclk = dev_priv->max_dotclk_freq; + int max_dotclk = dev_priv->display.max_dotclk_freq; int max_clock; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 035a55c8abec..f421bc69e197 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -160,10 +160,10 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, vlv_cck_get(dev_priv); - if (dev_priv->hpll_freq == 0) - dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); + if (dev_priv->display.hpll_freq == 0) + dev_priv->display.hpll_freq = vlv_get_hpll_vco(dev_priv); - hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); + hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->display.hpll_freq); vlv_cck_put(dev_priv); @@ -175,11 +175,11 @@ static void intel_update_czclk(struct drm_i915_private *dev_priv) if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) return; - dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", + dev_priv->display.czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", CCK_CZ_CLOCK_CONTROL); drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", - dev_priv->czclk_freq); + dev_priv->display.czclk_freq); } /* WA Display #0827: Gen9:all */ @@ -4006,7 +4006,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode; - int clock_limit = dev_priv->max_dotclk_freq; + int clock_limit = dev_priv->display.max_dotclk_freq; drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode); @@ -4046,7 +4046,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, */ if (intel_crtc_supports_double_wide(crtc) && pipe_mode->crtc_clock > clock_limit) { - clock_limit = dev_priv->max_dotclk_freq; + clock_limit = dev_priv->display.max_dotclk_freq; pipe_config->double_wide = true; } } diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 40a8e7cef42a..18f221d7f252 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -785,7 +785,7 @@ intel_dp_mode_valid(struct drm_connector *connector, struct drm_i915_private *dev_priv = to_i915(connector->dev); int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; - int max_dotclk = dev_priv->max_dotclk_freq; + int max_dotclk = dev_priv->display.max_dotclk_freq; u16 dsc_max_output_bpp = 0; u8 dsc_slice_count = 0; enum drm_mode_status status; @@ -1427,7 +1427,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.max_lane_count, limits.max_rate, limits.max_bpp, adjusted_mode->crtc_clock); - if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq || + if ((adjusted_mode->crtc_clock > i915->display.max_dotclk_freq || adjusted_mode->crtc_hdisplay > 5120) && intel_dp_can_bigjoiner(intel_dp)) pipe_config->bigjoiner = true; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d104441344c0..99a127e8704a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -683,7 +683,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; struct drm_dp_mst_port *port = intel_connector->port; const int min_bpp = 18; - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c index f453ceb8d149..1b96d2aa0730 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.c +++ b/drivers/gpu/drm/i915/display/intel_dsi.c @@ -59,7 +59,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_connector *intel_connector = to_intel_connector(connector); const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq; drm_dbg_kms(&dev_priv->drm, "\n"); diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 86c903e9df60..e06de60f4970 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -226,7 +226,7 @@ intel_dvo_mode_valid(struct drm_connector *connector, struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector)); const struct drm_display_mode *fixed_mode = to_intel_connector(connector)->panel.fixed_mode; - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq; int target_clock = mode->clock; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index aaa0207f483e..58dfa97304c4 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -104,14 +104,14 @@ void intel_fdi_pll_freq_update(struct drm_i915_private *i915) u32 fdi_pll_clk = intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; - i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; + i915->display.fdi_pll_freq = (fdi_pll_clk + 2) * 10000; } else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) { - i915->fdi_pll_freq = 270000; + i915->display.fdi_pll_freq = 270000; } else { return; } - drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq); + drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi_pll_freq); } int intel_fdi_link_freq(struct drm_i915_private *i915, @@ -120,7 +120,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915, if (HAS_DDI(i915)) return pipe_config->port_clock; /* SPLL */ else - return i915->fdi_pll_freq; + return i915->display.fdi_pll_freq; } int ilk_fdi_compute_config(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 1bc33766ed39..f536da3d05d8 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1950,7 +1950,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, struct drm_i915_private *dev_priv = to_i915(dev); enum drm_mode_status status; int clock = mode->clock; - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq; bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); bool ycbcr_420_only; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index e9fb402708a7..137e11cc40b5 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -388,7 +388,7 @@ intel_lvds_mode_valid(struct drm_connector *connector, { struct intel_connector *intel_connector = to_intel_connector(connector); struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; - int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; + int max_pixclk = to_i915(connector->dev)->display.max_dotclk_freq; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 6cb27599ea03..7691468571dc 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -1866,7 +1866,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector, struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq; bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state); int clock = mode->clock; diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index d02f09f7e750..c2f317aa5840 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -956,7 +956,7 @@ intel_tv_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c index 352989fefe60..c95754aed784 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c @@ -476,7 +476,7 @@ static int frequency_show(struct seq_file *m, void *unused) seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.max_cdclk_freq); - seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); + seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.max_dotclk_freq); intel_runtime_pm_put(uncore->rpm, wakeref); diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 799d382eea79..7fedff85e495 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -757,7 +757,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { mul = 1000000; - div = i915->czclk_freq; + div = i915->display.czclk_freq; overflow_hw = BIT_ULL(40); time_hw = vlv_residency_raw(uncore, reg); } else { diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index d812b27835f8..25f2767f582b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1514,7 +1514,7 @@ static void vlv_init_gpll_ref_freq(struct intel_rps *rps) rps->gpll_ref_freq = vlv_get_cck_clock(i915, "GPLL ref", CCK_GPLL_CLOCK_CONTROL, - i915->czclk_freq); + i915->display.czclk_freq); drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n", rps->gpll_ref_freq); @@ -1646,7 +1646,7 @@ static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir) time = ktime_us_delta(now.ktime, prev->ktime); - time *= rps_to_i915(rps)->czclk_freq; + time *= rps_to_i915(rps)->display.czclk_freq; /* Workload can be split between render + media, * e.g. SwapBuffers being blitted in X after being rendered in diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7610defe855b..37f5ab15a8d4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -577,7 +577,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->display.cdclk.hw.cdclk); seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->display.max_cdclk_freq); - seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); + seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->display.max_dotclk_freq); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); return 0; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b99a8edd1ca2..424d06cdc4d6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -840,6 +840,13 @@ struct drm_i915_display { struct intel_global_obj obj; } cdclk; unsigned int max_cdclk_freq; + + unsigned int skl_preferred_vco_freq; + + unsigned int max_dotclk_freq; + unsigned int hpll_freq; + unsigned int fdi_pll_freq; + unsigned int czclk_freq; }; struct drm_i915_private { @@ -951,12 +958,6 @@ struct drm_i915_private { struct mutex pps_mutex; unsigned int fsb_freq, mem_freq, is_ddr3; - unsigned int skl_preferred_vco_freq; - - unsigned int max_dotclk_freq; - unsigned int hpll_freq; - unsigned int fdi_pll_freq; - unsigned int czclk_freq; struct { /* The current hardware dbuf configuration */

[03/10] drm/i915: move more pll/clocks into display struct.

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