[04/10] drm/i915/display: move gmbus into display struct

Message ID	20210906034356.2946530-5-airlied@gmail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=0xFZ=N4=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 54C7660EB7 From: Dave Airlie <airlied@gmail.com> To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com> Date: Mon, 6 Sep 2021 13:43:50 +1000 Message-Id: <20210906034356.2946530-5-airlied@gmail.com> In-Reply-To: <20210906034356.2946530-1-airlied@gmail.com> References: <20210906034356.2946530-1-airlied@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="US-ASCII" Subject: [Intel-gfx] [PATCH 04/10] drm/i915/display: move gmbus into display struct Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	refactor display structs a little bit \| expand [RFC,00/10] refactor display structs a little bit [01/10] drm/i915: move display funcs into a display struct. [02/10] drm/i915/display: move cdclk info into display [03/10] drm/i915: move more pll/clocks into display struct. [04/10] drm/i915/display: move gmbus into display struct [05/10] drm/i915/display: move intel_dmc into display struct [06/10] drm/i915/display: move mipi_mmio_base to display struct [07/10] drm/i915/display: move pps_mmio_base to display struct [08/10] drm/i915/drrs: just use some local vars to simplify drrs code [09/10] drm/i915/display: move drrs into display struct [10/10] drm/i915/display: move fbc into display struct

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index e52f97c3ecab..f42e07824f01 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1948,12 +1948,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, * functions use cdclk. Not all platforms/ports do, * but we'll lock them all for simplicity. */ - mutex_lock(&dev_priv->gmbus_mutex); + mutex_lock(&dev_priv->display.gmbus_mutex); for_each_intel_dp(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, - &dev_priv->gmbus_mutex); + &dev_priv->display.gmbus_mutex); } dev_priv->display.funcs.set_cdclk(dev_priv, cdclk_config, pipe); @@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, mutex_unlock(&intel_dp->aux.hw_mutex); } - mutex_unlock(&dev_priv->gmbus_mutex); + mutex_unlock(&dev_priv->display.gmbus_mutex); for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index b0025dd3cb4a..8695da511e63 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -42,7 +42,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) bool done; #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) - done = wait_event_timeout(i915->gmbus_wait_queue, C, + done = wait_event_timeout(i915->display.gmbus_wait_queue, C, msecs_to_jiffies_timeout(timeout_ms)); /* just trace the final value */ diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index ceb1bf8a8c3c..9d31f5322f2a 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -347,7 +347,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) if (!HAS_GMBUS_IRQ(dev_priv)) irq_en = 0; - add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); + add_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait); intel_de_write_fw(dev_priv, GMBUS4, irq_en); status |= GMBUS_SATOER; @@ -358,7 +358,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 50); intel_de_write_fw(dev_priv, GMBUS4, 0); - remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); + remove_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait); if (gmbus2 & GMBUS_SATOER) return -ENXIO; @@ -378,7 +378,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) if (HAS_GMBUS_IRQ(dev_priv)) irq_enable = GMBUS_IDLE_EN; - add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); + add_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait); intel_de_write_fw(dev_priv, GMBUS4, irq_enable); ret = intel_wait_for_register_fw(&dev_priv->uncore, @@ -386,7 +386,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) 10); intel_de_write_fw(dev_priv, GMBUS4, 0); - remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); + remove_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait); return ret; } @@ -773,7 +773,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) int ret; wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); - mutex_lock(&dev_priv->gmbus_mutex); + mutex_lock(&dev_priv->display.gmbus_mutex); /* * In order to output Aksv to the receiver, use an indexed write to @@ -782,7 +782,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) */ ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); - mutex_unlock(&dev_priv->gmbus_mutex); + mutex_unlock(&dev_priv->display.gmbus_mutex); intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); return ret; @@ -808,7 +808,7 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter, struct intel_gmbus *bus = to_intel_gmbus(adapter); struct drm_i915_private *dev_priv = bus->dev_priv; - mutex_lock(&dev_priv->gmbus_mutex); + mutex_lock(&dev_priv->display.gmbus_mutex); } static int gmbus_trylock_bus(struct i2c_adapter *adapter, @@ -817,7 +817,7 @@ static int gmbus_trylock_bus(struct i2c_adapter *adapter, struct intel_gmbus *bus = to_intel_gmbus(adapter); struct drm_i915_private *dev_priv = bus->dev_priv; - return mutex_trylock(&dev_priv->gmbus_mutex); + return mutex_trylock(&dev_priv->display.gmbus_mutex); } static void gmbus_unlock_bus(struct i2c_adapter *adapter, @@ -826,7 +826,7 @@ static void gmbus_unlock_bus(struct i2c_adapter *adapter, struct intel_gmbus *bus = to_intel_gmbus(adapter); struct drm_i915_private *dev_priv = bus->dev_priv; - mutex_unlock(&dev_priv->gmbus_mutex); + mutex_unlock(&dev_priv->display.gmbus_mutex); } static const struct i2c_lock_operations gmbus_lock_ops = { @@ -847,22 +847,22 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv) int ret; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; + dev_priv->display.gpio_mmio_base = VLV_DISPLAY_BASE; else if (!HAS_GMCH(dev_priv)) /* * Broxton uses the same PCH offsets for South Display Engine, * even though it doesn't have a PCH. */ - dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; + dev_priv->display.gpio_mmio_base = PCH_DISPLAY_BASE; - mutex_init(&dev_priv->gmbus_mutex); - init_waitqueue_head(&dev_priv->gmbus_wait_queue); + mutex_init(&dev_priv->display.gmbus_mutex); + init_waitqueue_head(&dev_priv->display.gmbus_wait_queue); - for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { + for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus); pin++) { if (!intel_gmbus_is_valid_pin(dev_priv, pin)) continue; - bus = &dev_priv->gmbus[pin]; + bus = &dev_priv->display.gmbus[pin]; bus->adapter.owner = THIS_MODULE; bus->adapter.class = I2C_CLASS_DDC; @@ -906,7 +906,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv) if (!intel_gmbus_is_valid_pin(dev_priv, pin)) continue; - bus = &dev_priv->gmbus[pin]; + bus = &dev_priv->display.gmbus[pin]; i2c_del_adapter(&bus->adapter); } return ret; @@ -919,7 +919,7 @@ struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, !intel_gmbus_is_valid_pin(dev_priv, pin))) return NULL; - return &dev_priv->gmbus[pin].adapter; + return &dev_priv->display.gmbus[pin].adapter; } void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) @@ -934,7 +934,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) struct intel_gmbus *bus = to_intel_gmbus(adapter); struct drm_i915_private *dev_priv = bus->dev_priv; - mutex_lock(&dev_priv->gmbus_mutex); + mutex_lock(&dev_priv->display.gmbus_mutex); bus->force_bit += force_bit ? 1 : -1; drm_dbg_kms(&dev_priv->drm, @@ -942,7 +942,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) force_bit ? "en" : "dis", adapter->name, bus->force_bit); - mutex_unlock(&dev_priv->gmbus_mutex); + mutex_unlock(&dev_priv->display.gmbus_mutex); } bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) @@ -957,11 +957,11 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv) struct intel_gmbus *bus; unsigned int pin; - for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { + for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus); pin++) { if (!intel_gmbus_is_valid_pin(dev_priv, pin)) continue; - bus = &dev_priv->gmbus[pin]; + bus = &dev_priv->display.gmbus[pin]; i2c_del_adapter(&bus->adapter); } } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 424d06cdc4d6..20520402c246 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -847,6 +847,19 @@ struct drm_i915_display { unsigned int hpll_freq; unsigned int fdi_pll_freq; unsigned int czclk_freq; + + /** + * Base address of where the gmbus and gpio blocks are located (either + * on PCH or on SoC for platforms without PCH). + */ + u32 gpio_mmio_base; + + struct intel_gmbus gmbus[GMBUS_NUM_PINS]; + + /** gmbus_mutex protects against concurrent usage of the single hw gmbus + * controller on different i2c buses. */ + struct mutex gmbus_mutex; + wait_queue_head_t gmbus_wait_queue; }; struct drm_i915_private { @@ -899,25 +912,11 @@ struct drm_i915_private { struct intel_dmc dmc; - struct intel_gmbus gmbus[GMBUS_NUM_PINS]; - - /** gmbus_mutex protects against concurrent usage of the single hw gmbus - * controller on different i2c buses. */ - struct mutex gmbus_mutex; - - /** - * Base address of where the gmbus and gpio blocks are located (either - * on PCH or on SoC for platforms without PCH). - */ - u32 gpio_mmio_base; - /* MMIO base address for MIPI regs */ u32 mipi_mmio_base; u32 pps_mmio_base; - wait_queue_head_t gmbus_wait_queue; - struct pci_dev *bridge_dev; struct rb_root uabi_engines; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b1e3f51dc593..4ef644aeaf6c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1303,12 +1303,12 @@ static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, static void gmbus_irq_handler(struct drm_i915_private *dev_priv) { - wake_up_all(&dev_priv->gmbus_wait_queue); + wake_up_all(&dev_priv->display.gmbus_wait_queue); } static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) { - wake_up_all(&dev_priv->gmbus_wait_queue); + wake_up_all(&dev_priv->display.gmbus_wait_queue); } #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bd63760207b0..2e74c5c4699a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3403,7 +3403,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) /* * GPIO regs */ -#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ +#define GPIO(gpio) _MMIO(dev_priv->display.gpio_mmio_base + 0x5010 + \ 4 * (gpio)) # define GPIO_CLOCK_DIR_MASK (1 << 0) @@ -3421,7 +3421,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) # define GPIO_DATA_VAL_IN (1 << 12) # define GPIO_DATA_PULLUP_DISABLE (1 << 13) -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ +#define GMBUS0 _MMIO(dev_priv->display.gpio_mmio_base + 0x5100) /* clock/port select */ #define GMBUS_AKSV_SELECT (1 << 11) #define GMBUS_RATE_100KHZ (0 << 8) #define GMBUS_RATE_50KHZ (1 << 8) @@ -3430,7 +3430,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ +#define GMBUS1 _MMIO(dev_priv->display.gpio_mmio_base + 0x5104) /* command/status */ #define GMBUS_SW_CLR_INT (1 << 31) #define GMBUS_SW_RDY (1 << 30) #define GMBUS_ENT (1 << 29) /* enable timeout */ @@ -3445,7 +3445,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GMBUS_SLAVE_ADDR_SHIFT 1 #define GMBUS_SLAVE_READ (1 << 0) #define GMBUS_SLAVE_WRITE (0 << 0) -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ +#define GMBUS2 _MMIO(dev_priv->display.gpio_mmio_base + 0x5108) /* status */ #define GMBUS_INUSE (1 << 15) #define GMBUS_HW_WAIT_PHASE (1 << 14) #define GMBUS_STALL_TIMEOUT (1 << 13) @@ -3453,14 +3453,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GMBUS_HW_RDY (1 << 11) #define GMBUS_SATOER (1 << 10) #define GMBUS_ACTIVE (1 << 9) -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ +#define GMBUS3 _MMIO(dev_priv->display.gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ +#define GMBUS4 _MMIO(dev_priv->display.gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) #define GMBUS_NAK_EN (1 << 3) #define GMBUS_IDLE_EN (1 << 2) #define GMBUS_HW_WAIT_EN (1 << 1) #define GMBUS_HW_RDY_EN (1 << 0) -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ +#define GMBUS5 _MMIO(dev_priv->display.gpio_mmio_base + 0x5120) /* byte index */ #define GMBUS_2BYTE_INDEX_EN (1 << 31) /*

[04/10] drm/i915/display: move gmbus into display struct

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