@@ -1402,9 +1402,9 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
void intel_pps_setup(struct drm_i915_private *i915)
{
if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- i915->pps_mmio_base = PCH_PPS_BASE;
+ i915->display.pps_mmio_base = PCH_PPS_BASE;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- i915->pps_mmio_base = VLV_PPS_BASE;
+ i915->display.pps_mmio_base = VLV_PPS_BASE;
else
- i915->pps_mmio_base = PPS_BASE;
+ i915->display.pps_mmio_base = PPS_BASE;
}
@@ -857,6 +857,8 @@ struct drm_i915_display {
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
+ u32 pps_mmio_base;
+
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
@@ -915,8 +917,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- u32 pps_mmio_base;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
@@ -5166,7 +5166,7 @@ enum {
#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
#define PCH_PPS_BASE 0xC7200
-#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
+#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps_mmio_base - \
PPS_BASE + (reg) + \
(pps_idx) * 0x100)