[20/21] drm/i915: constify clock gating init vtable.

Message ID	20210908003944.2972024-21-airlied@gmail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=r3jS=N6=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 91E4961130 From: Dave Airlie <airlied@gmail.com> To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com> Date: Wed, 8 Sep 2021 10:39:43 +1000 Message-Id: <20210908003944.2972024-21-airlied@gmail.com> In-Reply-To: <20210908003944.2972024-1-airlied@gmail.com> References: <20210908003944.2972024-1-airlied@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="US-ASCII" Subject: [Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init vtable. Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	i915/display: split and constify vtable \| expand [00/21] i915/display: split and constify vtable [01/21] drm/i915/pm: drop get_fifo_size vfunc. [02/21] drm/i915: make update_wm take a dev_priv. [03/21] drm/i915/wm: move the update watermark wrapper to display side. [04/21] drm/i915: split clock gating init from display vtable [05/21] drm/i915: split watermark vfuncs from display vtable. [06/21] drm/i915: split color functions from display vtable [07/21] drm/i915: split audio functions from display vtable [08/21] drm/i915: split cdclk functions from display vtable. [09/21] drm/i915: split irq hotplug function from display vtable [10/21] drm/i915: split fdi link training from display vtable. [11/21] drm/i915: split the dpll clock compute out from display vtable. [12/21] drm/i915: constify fdi link training vtable [13/21] drm/i915: constify irq function vtable. [14/21] drm/i915: constify color function vtable. [15/21] drm/i915: constify the audio function vtable [16/21] drm/i915: constify the dpll clock vtable [17/21] drm/i915: constify the cdclk vtable [18/21] drm/i915: drop unused function ptr and comments. [19/21] drm/i915: constify display function vtable [20/21] drm/i915: constify clock gating init vtable. [21/21] drm/i915: constify display wm vtable

Message ID

20210908003944.2972024-21-airlied@gmail.com (mailing list archive)

State

New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 91E4961130
From: Dave Airlie <airlied@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@linux.intel.com,
	Dave Airlie <airlied@redhat.com>
Date: Wed,  8 Sep 2021 10:39:43 +1000
Message-Id: <20210908003944.2972024-21-airlied@gmail.com>
In-Reply-To: <20210908003944.2972024-1-airlied@gmail.com>
References: <20210908003944.2972024-1-airlied@gmail.com>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="US-ASCII"
Subject: [Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init
 vtable.
Precedence: list
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Series

i915/display: split and constify vtable | expand

Commit Message

Dave Airlie Sept. 8, 2021, 12:39 a.m. UTC

From: Dave Airlie <airlied@redhat.com>

I used a macro to avoid making any really silly mistakes here.
---
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c | 77 +++++++++++++++++++++++----------
 2 files changed, 54 insertions(+), 25 deletions(-)

Comments

Jani Nikula Sept. 8, 2021, noon UTC | #1

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> I used a macro to avoid making any really silly mistakes here.
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 77 +++++++++++++++++++++++----------
>  2 files changed, 54 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fbcafc7cc075..44094a25a110 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -990,7 +990,7 @@ struct drm_i915_private {
>  	struct workqueue_struct *flip_wq;
>  
>  	/* pm private clock gating functions */
> -	struct drm_i915_cg_funcs cg_funcs;
> +	const struct drm_i915_cg_funcs *cg_funcs;
>  
>  	/* pm display functions */
>  	struct drm_i915_wm_disp_funcs wm_disp;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a457646fb84..44f5582531ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	dev_priv->cg_funcs.init_clock_gating(dev_priv);
> +	dev_priv->cg_funcs->init_clock_gating(dev_priv);
>  }
>  
>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
> @@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  		    "No clock gating settings or workarounds applied.\n");
>  }
>  
> +#define CG_FUNCS(platform) \
> +static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
> +	.init_clock_gating = platform##_init_clock_gating     \
> +}
> +
> +CG_FUNCS(adlp);
> +CG_FUNCS(dg1);
> +CG_FUNCS(gen12lp);
> +CG_FUNCS(icl);
> +CG_FUNCS(cfl);
> +CG_FUNCS(skl);
> +CG_FUNCS(kbl);
> +CG_FUNCS(bxt);
> +CG_FUNCS(glk);
> +CG_FUNCS(bdw);
> +CG_FUNCS(chv);
> +CG_FUNCS(hsw);
> +CG_FUNCS(ivb);
> +CG_FUNCS(vlv);
> +CG_FUNCS(gen6);
> +CG_FUNCS(ilk);
> +CG_FUNCS(g4x);
> +CG_FUNCS(i965gm);
> +CG_FUNCS(i965g);
> +CG_FUNCS(gen3);
> +CG_FUNCS(i85x);
> +CG_FUNCS(i830);
> +CG_FUNCS(nop);

#undef CF_FUNCS

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +
>  /**
>   * intel_init_clock_gating_hooks - setup the clock gating hooks
>   * @dev_priv: device private
> @@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ALDERLAKE_P(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
> +		dev_priv->cg_funcs = &adlp_cg_funcs;
>  	else if (IS_DG1(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
> +		dev_priv->cg_funcs = &dg1_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 12)
> -		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
> +		dev_priv->cg_funcs = &gen12lp_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 11)
> -		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
> +		dev_priv->cg_funcs = &icl_cg_funcs;
>  	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
> +		dev_priv->cg_funcs = &cfl_cg_funcs;
>  	else if (IS_SKYLAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
> +		dev_priv->cg_funcs = &skl_cg_funcs;
>  	else if (IS_KABYLAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
> +		dev_priv->cg_funcs = &kbl_cg_funcs;
>  	else if (IS_BROXTON(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
> +		dev_priv->cg_funcs = &bxt_cg_funcs;
>  	else if (IS_GEMINILAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
> +		dev_priv->cg_funcs = &glk_cg_funcs;
>  	else if (IS_BROADWELL(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
> +		dev_priv->cg_funcs = &bdw_cg_funcs;
>  	else if (IS_CHERRYVIEW(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
> +		dev_priv->cg_funcs = &chv_cg_funcs;
>  	else if (IS_HASWELL(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
> +		dev_priv->cg_funcs = &hsw_cg_funcs;
>  	else if (IS_IVYBRIDGE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
> +		dev_priv->cg_funcs = &ivb_cg_funcs;
>  	else if (IS_VALLEYVIEW(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
> +		dev_priv->cg_funcs = &vlv_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 6)
> -		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
> +		dev_priv->cg_funcs = &gen6_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 5)
> -		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
> +		dev_priv->cg_funcs = &ilk_cg_funcs;
>  	else if (IS_G4X(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
> +		dev_priv->cg_funcs = &g4x_cg_funcs;
>  	else if (IS_I965GM(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
> +		dev_priv->cg_funcs = &i965gm_cg_funcs;
>  	else if (IS_I965G(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
> +		dev_priv->cg_funcs = &i965g_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 3)
> -		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
> +		dev_priv->cg_funcs = &gen3_cg_funcs;
>  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
> +		dev_priv->cg_funcs = &i85x_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 2)
> -		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
> +		dev_priv->cg_funcs = &i830_cg_funcs;
>  	else {
>  		MISSING_CASE(INTEL_DEVID(dev_priv));
> -		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
> +		dev_priv->cg_funcs = &nop_cg_funcs;
>  	}
>  }

Jani Nikula Sept. 8, 2021, noon UTC | #2

On Wed, 08 Sep 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
>> From: Dave Airlie <airlied@redhat.com>
>>
>> I used a macro to avoid making any really silly mistakes here.
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>>  drivers/gpu/drm/i915/intel_pm.c | 77 +++++++++++++++++++++++----------
>>  2 files changed, 54 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index fbcafc7cc075..44094a25a110 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -990,7 +990,7 @@ struct drm_i915_private {
>>  	struct workqueue_struct *flip_wq;
>>  
>>  	/* pm private clock gating functions */
>> -	struct drm_i915_cg_funcs cg_funcs;
>> +	const struct drm_i915_cg_funcs *cg_funcs;
>>  
>>  	/* pm display functions */
>>  	struct drm_i915_wm_disp_funcs wm_disp;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 7a457646fb84..44f5582531ac 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>>  
>>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	dev_priv->cg_funcs.init_clock_gating(dev_priv);
>> +	dev_priv->cg_funcs->init_clock_gating(dev_priv);
>>  }
>>  
>>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
>> @@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>>  		    "No clock gating settings or workarounds applied.\n");
>>  }
>>  
>> +#define CG_FUNCS(platform) \
>> +static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
>> +	.init_clock_gating = platform##_init_clock_gating     \
>> +}
>> +
>> +CG_FUNCS(adlp);
>> +CG_FUNCS(dg1);
>> +CG_FUNCS(gen12lp);
>> +CG_FUNCS(icl);
>> +CG_FUNCS(cfl);
>> +CG_FUNCS(skl);
>> +CG_FUNCS(kbl);
>> +CG_FUNCS(bxt);
>> +CG_FUNCS(glk);
>> +CG_FUNCS(bdw);
>> +CG_FUNCS(chv);
>> +CG_FUNCS(hsw);
>> +CG_FUNCS(ivb);
>> +CG_FUNCS(vlv);
>> +CG_FUNCS(gen6);
>> +CG_FUNCS(ilk);
>> +CG_FUNCS(g4x);
>> +CG_FUNCS(i965gm);
>> +CG_FUNCS(i965g);
>> +CG_FUNCS(gen3);
>> +CG_FUNCS(i85x);
>> +CG_FUNCS(i830);
>> +CG_FUNCS(nop);
>
> #undef CF_FUNCS

#undef CG_FUNCS, obviously.

>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> +
>>  /**
>>   * intel_init_clock_gating_hooks - setup the clock gating hooks
>>   * @dev_priv: device private
>> @@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>>  {
>>  	if (IS_ALDERLAKE_P(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
>> +		dev_priv->cg_funcs = &adlp_cg_funcs;
>>  	else if (IS_DG1(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
>> +		dev_priv->cg_funcs = &dg1_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 12)
>> -		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
>> +		dev_priv->cg_funcs = &gen12lp_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 11)
>> -		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
>> +		dev_priv->cg_funcs = &icl_cg_funcs;
>>  	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
>> +		dev_priv->cg_funcs = &cfl_cg_funcs;
>>  	else if (IS_SKYLAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
>> +		dev_priv->cg_funcs = &skl_cg_funcs;
>>  	else if (IS_KABYLAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
>> +		dev_priv->cg_funcs = &kbl_cg_funcs;
>>  	else if (IS_BROXTON(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
>> +		dev_priv->cg_funcs = &bxt_cg_funcs;
>>  	else if (IS_GEMINILAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
>> +		dev_priv->cg_funcs = &glk_cg_funcs;
>>  	else if (IS_BROADWELL(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
>> +		dev_priv->cg_funcs = &bdw_cg_funcs;
>>  	else if (IS_CHERRYVIEW(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
>> +		dev_priv->cg_funcs = &chv_cg_funcs;
>>  	else if (IS_HASWELL(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
>> +		dev_priv->cg_funcs = &hsw_cg_funcs;
>>  	else if (IS_IVYBRIDGE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
>> +		dev_priv->cg_funcs = &ivb_cg_funcs;
>>  	else if (IS_VALLEYVIEW(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
>> +		dev_priv->cg_funcs = &vlv_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 6)
>> -		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
>> +		dev_priv->cg_funcs = &gen6_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 5)
>> -		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
>> +		dev_priv->cg_funcs = &ilk_cg_funcs;
>>  	else if (IS_G4X(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
>> +		dev_priv->cg_funcs = &g4x_cg_funcs;
>>  	else if (IS_I965GM(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
>> +		dev_priv->cg_funcs = &i965gm_cg_funcs;
>>  	else if (IS_I965G(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
>> +		dev_priv->cg_funcs = &i965g_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 3)
>> -		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
>> +		dev_priv->cg_funcs = &gen3_cg_funcs;
>>  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
>> +		dev_priv->cg_funcs = &i85x_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 2)
>> -		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
>> +		dev_priv->cg_funcs = &i830_cg_funcs;
>>  	else {
>>  		MISSING_CASE(INTEL_DEVID(dev_priv));
>> -		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
>> +		dev_priv->cg_funcs = &nop_cg_funcs;
>>  	}
>>  }

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbcafc7cc075..44094a25a110 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -990,7 +990,7 @@  struct drm_i915_private {
 	struct workqueue_struct *flip_wq;
 
 	/* pm private clock gating functions */
-	struct drm_i915_cg_funcs cg_funcs;
+	const struct drm_i915_cg_funcs *cg_funcs;
 
 	/* pm display functions */
 	struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7a457646fb84..44f5582531ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@  static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
 
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	dev_priv->cg_funcs.init_clock_gating(dev_priv);
+	dev_priv->cg_funcs->init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7886,6 +7886,35 @@  static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 		    "No clock gating settings or workarounds applied.\n");
 }
 
+#define CG_FUNCS(platform) \
+static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
+	.init_clock_gating = platform##_init_clock_gating     \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+
 /**
  * intel_init_clock_gating_hooks - setup the clock gating hooks
  * @dev_priv: device private
@@ -7898,52 +7927,52 @@  static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ALDERLAKE_P(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
+		dev_priv->cg_funcs = &adlp_cg_funcs;
 	else if (IS_DG1(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
+		dev_priv->cg_funcs = &dg1_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 12)
-		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
+		dev_priv->cg_funcs = &gen12lp_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 11)
-		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
+		dev_priv->cg_funcs = &icl_cg_funcs;
 	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
+		dev_priv->cg_funcs = &cfl_cg_funcs;
 	else if (IS_SKYLAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
+		dev_priv->cg_funcs = &skl_cg_funcs;
 	else if (IS_KABYLAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
+		dev_priv->cg_funcs = &kbl_cg_funcs;
 	else if (IS_BROXTON(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
+		dev_priv->cg_funcs = &bxt_cg_funcs;
 	else if (IS_GEMINILAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
+		dev_priv->cg_funcs = &glk_cg_funcs;
 	else if (IS_BROADWELL(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
+		dev_priv->cg_funcs = &bdw_cg_funcs;
 	else if (IS_CHERRYVIEW(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
+		dev_priv->cg_funcs = &chv_cg_funcs;
 	else if (IS_HASWELL(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
+		dev_priv->cg_funcs = &hsw_cg_funcs;
 	else if (IS_IVYBRIDGE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
+		dev_priv->cg_funcs = &ivb_cg_funcs;
 	else if (IS_VALLEYVIEW(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
+		dev_priv->cg_funcs = &vlv_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 6)
-		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
+		dev_priv->cg_funcs = &gen6_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 5)
-		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
+		dev_priv->cg_funcs = &ilk_cg_funcs;
 	else if (IS_G4X(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
+		dev_priv->cg_funcs = &g4x_cg_funcs;
 	else if (IS_I965GM(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
+		dev_priv->cg_funcs = &i965gm_cg_funcs;
 	else if (IS_I965G(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
+		dev_priv->cg_funcs = &i965g_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 3)
-		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
+		dev_priv->cg_funcs = &gen3_cg_funcs;
 	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
+		dev_priv->cg_funcs = &i85x_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 2)
-		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
+		dev_priv->cg_funcs = &i830_cg_funcs;
 	else {
 		MISSING_CASE(INTEL_DEVID(dev_priv));
-		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
+		dev_priv->cg_funcs = &nop_cg_funcs;
 	}
 }

[20/21] drm/i915: constify clock gating init vtable.

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