From patchwork Wed Sep 8 00:39:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Airlie X-Patchwork-Id: 12479667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1A11C433F5 for ; Wed, 8 Sep 2021 00:40:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91E4961130 for ; Wed, 8 Sep 2021 00:40:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 91E4961130 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E91556E105; Wed, 8 Sep 2021 00:40:39 +0000 (UTC) Received: from us-smtp-delivery-44.mimecast.com (us-smtp-delivery-44.mimecast.com [205.139.111.44]) by gabe.freedesktop.org (Postfix) with ESMTPS id 376356E105 for ; Wed, 8 Sep 2021 00:40:39 +0000 (UTC) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-420-26KXf9Z3PXeuHUn3DRuKsw-1; Tue, 07 Sep 2021 20:40:34 -0400 X-MC-Unique: 26KXf9Z3PXeuHUn3DRuKsw-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1F65E107ACC7; Wed, 8 Sep 2021 00:40:34 +0000 (UTC) Received: from dreadlord-bne-redhat-com.bne.redhat.com (unknown [10.64.0.157]) by smtp.corp.redhat.com (Postfix) with ESMTP id CE07560CD1; Wed, 8 Sep 2021 00:40:32 +0000 (UTC) From: Dave Airlie To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, Dave Airlie Date: Wed, 8 Sep 2021 10:39:43 +1000 Message-Id: <20210908003944.2972024-21-airlied@gmail.com> In-Reply-To: <20210908003944.2972024-1-airlied@gmail.com> References: <20210908003944.2972024-1-airlied@gmail.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: gmail.com Subject: [Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init vtable. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dave Airlie I used a macro to avoid making any really silly mistakes here. Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 77 +++++++++++++++++++++++---------- 2 files changed, 54 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fbcafc7cc075..44094a25a110 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -990,7 +990,7 @@ struct drm_i915_private { struct workqueue_struct *flip_wq; /* pm private clock gating functions */ - struct drm_i915_cg_funcs cg_funcs; + const struct drm_i915_cg_funcs *cg_funcs; /* pm display functions */ struct drm_i915_wm_disp_funcs wm_disp; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7a457646fb84..44f5582531ac 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv) void intel_init_clock_gating(struct drm_i915_private *dev_priv) { - dev_priv->cg_funcs.init_clock_gating(dev_priv); + dev_priv->cg_funcs->init_clock_gating(dev_priv); } void intel_suspend_hw(struct drm_i915_private *dev_priv) @@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) "No clock gating settings or workarounds applied.\n"); } +#define CG_FUNCS(platform) \ +static const struct drm_i915_cg_funcs platform##_cg_funcs = { \ + .init_clock_gating = platform##_init_clock_gating \ +} + +CG_FUNCS(adlp); +CG_FUNCS(dg1); +CG_FUNCS(gen12lp); +CG_FUNCS(icl); +CG_FUNCS(cfl); +CG_FUNCS(skl); +CG_FUNCS(kbl); +CG_FUNCS(bxt); +CG_FUNCS(glk); +CG_FUNCS(bdw); +CG_FUNCS(chv); +CG_FUNCS(hsw); +CG_FUNCS(ivb); +CG_FUNCS(vlv); +CG_FUNCS(gen6); +CG_FUNCS(ilk); +CG_FUNCS(g4x); +CG_FUNCS(i965gm); +CG_FUNCS(i965g); +CG_FUNCS(gen3); +CG_FUNCS(i85x); +CG_FUNCS(i830); +CG_FUNCS(nop); + /** * intel_init_clock_gating_hooks - setup the clock gating hooks * @dev_priv: device private @@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { if (IS_ALDERLAKE_P(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating; + dev_priv->cg_funcs = &adlp_cg_funcs; else if (IS_DG1(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating; + dev_priv->cg_funcs = &dg1_cg_funcs; else if (GRAPHICS_VER(dev_priv) == 12) - dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating; + dev_priv->cg_funcs = &gen12lp_cg_funcs; else if (GRAPHICS_VER(dev_priv) == 11) - dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating; + dev_priv->cg_funcs = &icl_cg_funcs; else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating; + dev_priv->cg_funcs = &cfl_cg_funcs; else if (IS_SKYLAKE(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating; + dev_priv->cg_funcs = &skl_cg_funcs; else if (IS_KABYLAKE(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating; + dev_priv->cg_funcs = &kbl_cg_funcs; else if (IS_BROXTON(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating; + dev_priv->cg_funcs = &bxt_cg_funcs; else if (IS_GEMINILAKE(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating; + dev_priv->cg_funcs = &glk_cg_funcs; else if (IS_BROADWELL(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating; + dev_priv->cg_funcs = &bdw_cg_funcs; else if (IS_CHERRYVIEW(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating; + dev_priv->cg_funcs = &chv_cg_funcs; else if (IS_HASWELL(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating; + dev_priv->cg_funcs = &hsw_cg_funcs; else if (IS_IVYBRIDGE(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating; + dev_priv->cg_funcs = &ivb_cg_funcs; else if (IS_VALLEYVIEW(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating; + dev_priv->cg_funcs = &vlv_cg_funcs; else if (GRAPHICS_VER(dev_priv) == 6) - dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating; + dev_priv->cg_funcs = &gen6_cg_funcs; else if (GRAPHICS_VER(dev_priv) == 5) - dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating; + dev_priv->cg_funcs = &ilk_cg_funcs; else if (IS_G4X(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating; + dev_priv->cg_funcs = &g4x_cg_funcs; else if (IS_I965GM(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating; + dev_priv->cg_funcs = &i965gm_cg_funcs; else if (IS_I965G(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating; + dev_priv->cg_funcs = &i965g_cg_funcs; else if (GRAPHICS_VER(dev_priv) == 3) - dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating; + dev_priv->cg_funcs = &gen3_cg_funcs; else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) - dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating; + dev_priv->cg_funcs = &i85x_cg_funcs; else if (GRAPHICS_VER(dev_priv) == 2) - dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating; + dev_priv->cg_funcs = &i830_cg_funcs; else { MISSING_CASE(INTEL_DEVID(dev_priv)); - dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating; + dev_priv->cg_funcs = &nop_cg_funcs; } }