[07/23] drm/i915: split watermark vfuncs from display vtable.

Message ID	20210909015322.2988500-8-airlied@gmail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=8Ejf=N7=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6931460187 From: Dave Airlie <airlied@gmail.com> To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com> Date: Thu, 9 Sep 2021 11:53:06 +1000 Message-Id: <20210909015322.2988500-8-airlied@gmail.com> In-Reply-To: <20210909015322.2988500-1-airlied@gmail.com> References: <20210909015322.2988500-1-airlied@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="US-ASCII" Subject: [Intel-gfx] [PATCH 07/23] drm/i915: split watermark vfuncs from display vtable. Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	i915/display: split and constify vtable (v3) \| expand [00/23] i915/display: split and constify vtable (v3) [01/23] drm/i915/pm: drop get_fifo_size vfunc. [02/23] drm/i915: make update_wm take a dev_priv. [03/23] drm/i915/wm: provide wrappers around watermark vfuncs calls [04/23] drm/i915: add wrappers around cdclk vtable funcs. [05/23] drm/i915/display: add intel_fdi_link_train wrapper. [06/23] drm/i915: split clock gating init from display vtable [07/23] drm/i915: split watermark vfuncs from display vtable. [08/23] drm/i915: split color functions from display vtable [09/23] drm/i915: split audio functions from display vtable [10/23] drm/i915: split cdclk functions from display vtable. [11/23] drm/i915: split irq hotplug function from display vtable [12/23] drm/i915: split fdi link training from display vtable. [13/23] drm/i915: split the dpll clock compute out from display vtable. [14/23] drm/i915: constify fdi link training vtable [15/23] drm/i915: constify hotplug function vtable. [16/23] drm/i915: constify color function vtable. [17/23] drm/i915: constify the audio function vtable [18/23] drm/i915: constify the dpll clock vtable [19/23] drm/i915: constify the cdclk vtable [20/23] drm/i915: drop unused function ptr and comments. [21/23] drm/i915: constify display function vtable [22/23] drm/i915: constify clock gating init vtable. [23/23] drm/i915: constify display wm vtable

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f2678d26cd17..413bc4667e47 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev, */ static void intel_update_watermarks(struct drm_i915_private *dev_priv) { - if (dev_priv->display.update_wm) - dev_priv->display.update_wm(dev_priv); + if (dev_priv->wm_disp.update_wm) + dev_priv->wm_disp.update_wm(dev_priv); } static int intel_compute_pipe_wm(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (dev_priv->display.compute_pipe_wm) - return dev_priv->display.compute_pipe_wm(state, crtc); + if (dev_priv->wm_disp.compute_pipe_wm) + return dev_priv->wm_disp.compute_pipe_wm(state, crtc); return 0; } @@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state, { struct drm_i915_private *dev_priv = to_i915(state->base.dev); if (drm_WARN_ON(&dev_priv->drm, - !dev_priv->display.compute_pipe_wm)) + !dev_priv->wm_disp.compute_pipe_wm)) return 0; - if (dev_priv->display.compute_pipe_wm) - return dev_priv->display.compute_intermediate_wm(state, crtc); + if (dev_priv->wm_disp.compute_pipe_wm) + return dev_priv->wm_disp.compute_intermediate_wm(state, crtc); return 0; } @@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (dev_priv->display.initial_watermarks) { - dev_priv->display.initial_watermarks(state, crtc); + if (dev_priv->wm_disp.initial_watermarks) { + dev_priv->wm_disp.initial_watermarks(state, crtc); return true; } return false; @@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (dev_priv->display.atomic_update_watermarks) - dev_priv->display.atomic_update_watermarks(state, crtc); + if (dev_priv->wm_disp.atomic_update_watermarks) + dev_priv->wm_disp.atomic_update_watermarks(state, crtc); } static void intel_optimize_watermarks(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (dev_priv->display.optimize_watermarks) - dev_priv->display.optimize_watermarks(state, crtc); + if (dev_priv->wm_disp.optimize_watermarks) + dev_priv->wm_disp.optimize_watermarks(state, crtc); } static void intel_compute_global_watermarks(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (dev_priv->display.compute_global_watermarks) - dev_priv->display.compute_global_watermarks(state); + if (dev_priv->wm_disp.compute_global_watermarks) + dev_priv->wm_disp.compute_global_watermarks(state); } /* returns HPLL frequency in kHz */ @@ -3669,6 +3669,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, if (!intel_initial_watermarks(state, crtc)) intel_update_watermarks(dev_priv); + intel_enable_pipe(new_crtc_state); intel_crtc_vblank_on(new_crtc_state); @@ -3734,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) != 2) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - if (!dev_priv->display.initial_watermarks) + if (!dev_priv->wm_disp.initial_watermarks) intel_update_watermarks(dev_priv); /* clock the pipe down to 640x480@60 to potentially save power */ @@ -11387,7 +11388,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv) int i; /* Only supported on platforms that use atomic watermark design */ - if (!dev_priv->display.optimize_watermarks) + if (!dev_priv->wm_disp.optimize_watermarks) return; state = drm_atomic_state_alloc(&dev_priv->drm); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 48d30b967def..e70587cf8679 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -328,13 +328,10 @@ struct drm_i915_clock_gating_funcs { void (*init_clock_gating)(struct drm_i915_private *dev_priv); }; -struct drm_i915_display_funcs { - void (*get_cdclk)(struct drm_i915_private *dev_priv, - struct intel_cdclk_config *cdclk_config); - void (*set_cdclk)(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *cdclk_config, - enum pipe pipe); - int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); +/* functions used for watermark calcs for display. */ +struct drm_i915_wm_disp_funcs { + /* update_wm is for legacy wm management */ + void (*update_wm)(struct drm_i915_private *dev_priv); int (*compute_pipe_wm)(struct intel_atomic_state *state, struct intel_crtc *crtc); int (*compute_intermediate_wm)(struct intel_atomic_state *state, @@ -346,7 +343,15 @@ struct drm_i915_display_funcs { void (*optimize_watermarks)(struct intel_atomic_state *state, struct intel_crtc *crtc); int (*compute_global_watermarks)(struct intel_atomic_state *state); - void (*update_wm)(struct drm_i915_private *dev_priv); +}; + +struct drm_i915_display_funcs { + void (*get_cdclk)(struct drm_i915_private *dev_priv, + struct intel_cdclk_config *cdclk_config); + void (*set_cdclk)(struct drm_i915_private *dev_priv, + const struct intel_cdclk_config *cdclk_config, + enum pipe pipe); + int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); u8 (*calc_voltage_level)(int cdclk); /* Returns the active state of the crtc, and if the crtc is active, @@ -961,6 +966,9 @@ struct drm_i915_private { /* pm private clock gating functions */ struct drm_i915_clock_gating_funcs clock_gating_funcs; + /* pm display functions */ + struct drm_i915_wm_disp_funcs wm_disp; + /* Display functions */ struct drm_i915_display_funcs display; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index add50ff01d7c..826216a115fd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7962,7 +7962,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) /* For FIFO watermark updates */ if (DISPLAY_VER(dev_priv) >= 9) { skl_setup_wm_latency(dev_priv); - dev_priv->display.compute_global_watermarks = skl_compute_wm; + dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm; } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_setup_wm_latency(dev_priv); @@ -7970,12 +7970,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv) dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] && dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { - dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; - dev_priv->display.compute_intermediate_wm = + dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm; + dev_priv->wm_disp.compute_intermediate_wm = ilk_compute_intermediate_wm; - dev_priv->display.initial_watermarks = + dev_priv->wm_disp.initial_watermarks = ilk_initial_watermarks; - dev_priv->display.optimize_watermarks = + dev_priv->wm_disp.optimize_watermarks = ilk_optimize_watermarks; } else { drm_dbg_kms(&dev_priv->drm, @@ -7984,17 +7984,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv) } } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_setup_wm_latency(dev_priv); - dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm; - dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm; - dev_priv->display.initial_watermarks = vlv_initial_watermarks; - dev_priv->display.optimize_watermarks = vlv_optimize_watermarks; - dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo; + dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm; + dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm; + dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks; + dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks; + dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo; } else if (IS_G4X(dev_priv)) { g4x_setup_wm_latency(dev_priv); - dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm; - dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm; - dev_priv->display.initial_watermarks = g4x_initial_watermarks; - dev_priv->display.optimize_watermarks = g4x_optimize_watermarks; + dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm; + dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm; + dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks; + dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks; } else if (IS_PINEVIEW(dev_priv)) { if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv), dev_priv->is_ddr3, @@ -8008,18 +8008,18 @@ void intel_init_pm(struct drm_i915_private *dev_priv) dev_priv->fsb_freq, dev_priv->mem_freq); /* Disable CxSR and never update its watermark again */ intel_set_memory_cxsr(dev_priv, false); - dev_priv->display.update_wm = NULL; + dev_priv->wm_disp.update_wm = NULL; } else - dev_priv->display.update_wm = pnv_update_wm; + dev_priv->wm_disp.update_wm = pnv_update_wm; } else if (DISPLAY_VER(dev_priv) == 4) { - dev_priv->display.update_wm = i965_update_wm; + dev_priv->wm_disp.update_wm = i965_update_wm; } else if (DISPLAY_VER(dev_priv) == 3) { - dev_priv->display.update_wm = i9xx_update_wm; + dev_priv->wm_disp.update_wm = i9xx_update_wm; } else if (DISPLAY_VER(dev_priv) == 2) { if (INTEL_NUM_PIPES(dev_priv) == 1) - dev_priv->display.update_wm = i845_update_wm; + dev_priv->wm_disp.update_wm = i845_update_wm; else - dev_priv->display.update_wm = i9xx_update_wm; + dev_priv->wm_disp.update_wm = i9xx_update_wm; } else { drm_err(&dev_priv->drm, "unexpected fall-through in %s\n", __func__);

[07/23] drm/i915: split watermark vfuncs from display vtable.

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Patch