| Message ID | 20210923194617.69136-2-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/7] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe | expand |
Looks good to me. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> On 9/23/21 10:46 PM, José Roberto de Souza wrote: > CURSURFLIVE writes has no affect when PSR2 selective fetch is enabled, > the right thing to do here would be calculate the damaged area and > program PSR2 selective fetch registers properly during vblank but > we can't do that due to performance reasons. > > So for now we can workaround and offer proper rendering by disabling > PSR2 and enabling in the worker a few miliseconds later if there is > no other frontbuffer rendering. > > This approach will eat some of the PSR2 power savings when userspace > makes use of frontbuffer rendering but that is the solution that we > can offer to enable PSR2 selective fetch right now while we work in > the proper solution for frontbuffer rendering and PSR2. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index a2e4ef42be60a..ba2da689920f9 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1413,6 +1413,12 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > + /* CURSURFLIVE has no effect when Selective fetch is enabled */ > + if (intel_dp->psr.psr2_sel_fetch_enabled) { > + intel_psr_exit(intel_dp); > + return; > + } > + > /* > * Display WA #0884: skl+ > * This documented WA for bxt can be safely applied >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a2e4ef42be60a..ba2da689920f9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1413,6 +1413,12 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + /* CURSURFLIVE has no effect when Selective fetch is enabled */ + if (intel_dp->psr.psr2_sel_fetch_enabled) { + intel_psr_exit(intel_dp); + return; + } + /* * Display WA #0884: skl+ * This documented WA for bxt can be safely applied
CURSURFLIVE writes has no affect when PSR2 selective fetch is enabled, the right thing to do here would be calculate the damaged area and program PSR2 selective fetch registers properly during vblank but we can't do that due to performance reasons. So for now we can workaround and offer proper rendering by disabling PSR2 and enabling in the worker a few miliseconds later if there is no other frontbuffer rendering. This approach will eat some of the PSR2 power savings when userspace makes use of frontbuffer rendering but that is the solution that we can offer to enable PSR2 selective fetch right now while we work in the proper solution for frontbuffer rendering and PSR2. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++ 1 file changed, 6 insertions(+)