From patchwork Thu Sep 23 19:46:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12513609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33928C433F5 for ; Thu, 23 Sep 2021 19:40:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC02D61241 for ; Thu, 23 Sep 2021 19:40:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EC02D61241 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B84B6E10B; Thu, 23 Sep 2021 19:40:45 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B5D6E6E10B for ; Thu, 23 Sep 2021 19:40:43 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10116"; a="223970610" X-IronPort-AV: E=Sophos;i="5.85,317,1624345200"; d="scan'208";a="223970610" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2021 12:40:43 -0700 X-IronPort-AV: E=Sophos;i="5.85,317,1624345200"; d="scan'208";a="455236742" Received: from josouza-mobl2.jf.intel.com (HELO josouza-mobl2.intel.com) ([10.24.14.60]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2021 12:40:43 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Cc: Gwan-gyeong Mun , =?utf-8?b?VmlsbGUgU3lyasOk?= =?utf-8?b?bMOk?= , =?utf-8?q?Jos=C3=A9_Rober?= =?utf-8?q?to_de_Souza?= Date: Thu, 23 Sep 2021 12:46:12 -0700 Message-Id: <20210923194617.69136-2-jose.souza@intel.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923194617.69136-1-jose.souza@intel.com> References: <20210923194617.69136-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/7] drm/i915/display: Handle frontbuffer rendering when PSR2 selective fetch is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" CURSURFLIVE writes has no affect when PSR2 selective fetch is enabled, the right thing to do here would be calculate the damaged area and program PSR2 selective fetch registers properly during vblank but we can't do that due to performance reasons. So for now we can workaround and offer proper rendering by disabling PSR2 and enabling in the worker a few miliseconds later if there is no other frontbuffer rendering. This approach will eat some of the PSR2 power savings when userspace makes use of frontbuffer rendering but that is the solution that we can offer to enable PSR2 selective fetch right now while we work in the proper solution for frontbuffer rendering and PSR2. Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a2e4ef42be60a..ba2da689920f9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1413,6 +1413,12 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + /* CURSURFLIVE has no effect when Selective fetch is enabled */ + if (intel_dp->psr.psr2_sel_fetch_enabled) { + intel_psr_exit(intel_dp); + return; + } + /* * Display WA #0884: skl+ * This documented WA for bxt can be safely applied