| Message ID | 20210923194617.69136-6-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/7] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe | expand |
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> On 9/23/21 10:46 PM, José Roberto de Souza wrote: > With all the recent fixes PSR2 is properly working in Alderlake-P but > due to some issues that don't have software workarounds it will not be > supported in display steppings older than B0. > > Even with this patch PSR2 will no be enabled by default in ADL-P, it > still requires enable_psr2_sel_fetch to be set to true, what some > of our tests does. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------ > 1 file changed, 2 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 001d81f128989..37727ff2b2ec9 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -830,12 +830,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > - /* > - * We are missing the implementation of some workarounds to enabled PSR2 > - * in Alderlake_P, until ready PSR2 should be kept disabled. > - */ > - if (IS_ALDERLAKE_P(dev_priv)) { > - drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n"); > + if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > + drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); > return false; > } > >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 001d81f128989..37727ff2b2ec9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -830,12 +830,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - /* - * We are missing the implementation of some workarounds to enabled PSR2 - * in Alderlake_P, until ready PSR2 should be kept disabled. - */ - if (IS_ALDERLAKE_P(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n"); + if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { + drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); return false; }
With all the recent fixes PSR2 is properly working in Alderlake-P but due to some issues that don't have software workarounds it will not be supported in display steppings older than B0. Even with this patch PSR2 will no be enabled by default in ADL-P, it still requires enable_psr2_sel_fetch to be set to true, what some of our tests does. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)