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Mon, 27 Sep 2021 10:41:19 -0500 From: Fangzhi Zuo To: , , , CC: , , , Fangzhi Zuo Date: Mon, 27 Sep 2021 11:39:41 -0400 Message-ID: <20210927153941.2231704-1-Jerry.Zuo@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8b8a0a3c-c58a-4232-97fb-08d981cd42d2 X-MS-TrafficTypeDiagnostic: MWHPR12MB1886: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: REtI7GR5AtOz4Hlwl/1Fmkw7yyE4u4o5CjUDux8aYLAtkrklL/ayoW4H30//6iJKKItOE0mRiNY2R9HpQs1vMDFs/i8KaZXCVNvFShKWv00LhSMhESd6yNSnkqU9p/30hNUluapzjxFXKZweLXot77bdSZXg+Ze0tzCgXaIgjRzsKMkmFJn808sO530uML53fIXRjh3Ge2nnx22AsKUYLl8UedQ+kWhUNvdiyL/xcq7lzL7gV2igxZx30X0zHLg8eANOOTSb+pybsAlKYzTFDpyCrASGPWkk1MuUGeuZm0798e6rAKS3M+PS1ydjl26eeLPaav9w0ZiCFI+oifMQhJbu1biZ3POtbxZyhbbz79WdlEuvCPrAPHfenq9eYVpx3ujhgfBIdJxIdqJfVA07cuZZcgdCjXcA5rbOdKAfWjWjnlkiF2AWQynvO25Jo/uxCdpTUbaJQLaNtolEuciXfdsJtCdwQNPGVI8WIBmJxv0Emwye+DdZ1sasBE9TLsbL5YqgpK5aqG/ORbAWdl/LuPpJHMNKwC7OCl/pzMNqvnZf+t+hiJvjqtmQ6Em9EX4EZfOp98o/lpk+EhpUBSPy8i3n4BRpJ0TQY4IjMA/Lu555FVBZwsNeBb3iUDXSf/nRd1u5Nu82Q2TkObZWxq5TVbOrJd6LdLfPLQOENwNyc22aH/hTDpJ2hMzmA/6ZAyX7kxy1xG5S5oq5RKh/2VAFCjOpuP+Arfz6AikNdYPIUOykKX6uR60lzPEMxGwQRoUS X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(8676002)(110136005)(8936002)(47076005)(2616005)(70206006)(508600001)(426003)(36756003)(6666004)(356005)(70586007)(336012)(83380400001)(7696005)(5660300002)(2906002)(316002)(36860700001)(4326008)(54906003)(81166007)(1076003)(26005)(82310400003)(86362001)(186003)(21314003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2021 15:41:23.8572 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b8a0a3c-c58a-4232-97fb-08d981cd42d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1886 X-Mailman-Approved-At: Mon, 27 Sep 2021 17:42:59 +0000 Subject: [Intel-gfx] [PATCH v2] drm/dp: Add Additional DP2 Headers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Include FEC, DSC, Link Training related headers. Signed-off-by: Fangzhi Zuo --- This patch is based on top of the other DP2.0 work in "drm/dp: add LTTPR DP 2.0 DPCD addresses" --- include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f1fd9889f190 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -453,6 +453,7 @@ struct drm_panel; # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ @@ -537,6 +538,9 @@ struct drm_panel; #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 +/* DFP Capability Extension */ +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -688,6 +692,7 @@ struct drm_panel; #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ # define DP_DECOMPRESSION_EN (1 << 0) +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE BIT(0) @@ -743,6 +748,7 @@ struct drm_panel; # define DP_RECEIVE_PORT_0_STATUS (1 << 0) # define DP_RECEIVE_PORT_1_STATUS (1 << 1) # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ #define DP_ADJUST_REQUEST_LANE0_1 0x206 #define DP_ADJUST_REQUEST_LANE2_3 0x207 @@ -865,6 +871,8 @@ struct drm_panel; # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 # define DP_PHY_TEST_PATTERN_CP2520 0x5 +#define DP_PHY_SQUARE_PATTERN 0x249 + #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 @@ -1109,6 +1117,18 @@ struct drm_panel; #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 + +/* DSC Extended Capability Branch Total DSC Resources */ +#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 /* 2.0 */ +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +# define DP_DSC_DECODER_COUNT_SHIFT 5 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 + /* Protocol Converter Extension */ /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ #define DP_CEC_TUNNELING_CAPABILITY 0x3000