From patchwork Thu Sep 30 00:14:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12527025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3DA7C433EF for ; Thu, 30 Sep 2021 00:09:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A467A61439 for ; Thu, 30 Sep 2021 00:09:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A467A61439 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B1026EB12; Thu, 30 Sep 2021 00:09:11 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 695A36E2B4 for ; Thu, 30 Sep 2021 00:08:46 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10122"; a="212148104" X-IronPort-AV: E=Sophos;i="5.85,334,1624345200"; d="scan'208";a="212148104" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 17:08:30 -0700 X-IronPort-AV: E=Sophos;i="5.85,334,1624345200"; d="scan'208";a="438658513" Received: from josouza-mobl2.jf.intel.com (HELO josouza-mobl2.intel.com) ([10.24.14.60]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 17:08:30 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= Date: Wed, 29 Sep 2021 17:14:09 -0700 Message-Id: <20210930001409.254817-9-jose.souza@intel.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210930001409.254817-1-jose.souza@intel.com> References: <20210930001409.254817-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 9/9] drm/i915/display: Always wait vblank counter to increment when commit needs a modeset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Not waiting for vblank counter to increment could potentialy cause issues as commits after the one that needs a modeset could change state of entities that are not committed into hardware yet. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9e9db1b0a907b..9c49b6031cb5e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10494,15 +10494,24 @@ static int intel_atomic_commit(struct drm_device *dev, * FIXME doing watermarks and fb cleanup from a vblank worker * (assuming we had any) would solve these problems. */ - if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { + if (state->base.legacy_cursor_update) { struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int i; - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) - if (new_crtc_state->wm.need_postvbl_update || - new_crtc_state->update_wm_post) + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (intel_crtc_needs_modeset(new_crtc_state)) { + state->base.legacy_cursor_update = false; + break; + } + + if (DISPLAY_VER(dev_priv) < 9 && + (new_crtc_state->wm.need_postvbl_update || + new_crtc_state->update_wm_post)) { state->base.legacy_cursor_update = false; + break; + } + } } ret = intel_atomic_prepare_commit(state);