From patchwork Tue Nov 2 02:12:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12597763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BC35C433EF for ; Tue, 2 Nov 2021 02:25:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56262600D4 for ; Tue, 2 Nov 2021 02:25:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 56262600D4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD0936ED02; Tue, 2 Nov 2021 02:25:45 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6FAC36ED02 for ; Tue, 2 Nov 2021 02:25:44 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10155"; a="229887874" X-IronPort-AV: E=Sophos;i="5.87,201,1631602800"; d="scan'208";a="229887874" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2021 19:06:09 -0700 X-IronPort-AV: E=Sophos;i="5.87,201,1631602800"; d="scan'208";a="727705526" Received: from linchunh-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.212.101.233]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2021 19:06:09 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 1 Nov 2021 19:12:33 -0700 Message-Id: <20211102021233.215980-1-jose.souza@intel.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Exit PSR when doing async flips X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Changing the buffer in the middle of the scanout then entering an period of flip idleness will cause part of the previous buffer being diplayed to user when PSR is enabled. So here disabling and scheduling activation after a few milliseconds when async flip is enabled in the state. The async flip check that we had in PSR compute is not executed at every flip so it was not doing anything useful and is also being dropped here. v2: - scheduling the PSR work in _intel_psr_post_plane_update() Cc: Karthik B S Cc: Vandita Kulkarni Cc: Ville Syrjälä Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9d589d471e335..e1338f5b2967c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -731,12 +731,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, return false; } - if (crtc_state->uapi.async_flip) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 sel fetch not enabled, async flip enabled\n"); - return false; - } - /* Wa_14010254185 Wa_14010103792 */ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { drm_dbg_kms(&dev_priv->drm, @@ -1780,6 +1774,9 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, if (psr->enabled && needs_to_disable) intel_psr_disable_locked(intel_dp); + if (psr->enabled && crtc_state->uapi.async_flip) + intel_psr_exit(intel_dp); + mutex_unlock(&psr->lock); } } @@ -1810,6 +1807,9 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, if (crtc_state->crc_enabled && psr->enabled) psr_force_hw_tracking_exit(intel_dp); + if (psr->enabled && !psr->active && crtc_state->uapi.async_flip) + schedule_work(&intel_dp->psr.work); + mutex_unlock(&psr->lock); } }