| Message ID | 20211109120428.15211-1-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Revert "drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping" | expand |
On Tue, 09 Nov 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > This reverts commit 991d9557b0c457fb92bc49ddde24a7d9ce6144a8. > The Bspec was updated recently with the pll ungate sequence > similar to that of icl dsi enable sequence. > Hence reverting. > > Bspec:49187 Please add a space after : in the Bspec tag, and please add a Fixes: tag while applying. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++-------- > 1 file changed, 2 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index 2337c0b54586..edc38fbd2545 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -698,10 +698,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); > > for_each_dsi_phy(phy, intel_dsi->phys) { > - if (DISPLAY_VER(dev_priv) >= 12) > - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > - else > - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > } > intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); > > @@ -1137,8 +1134,6 @@ static void > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > /* step 4a: power up all lanes of the DDI used by DSI */ > gen11_dsi_power_up_lanes(encoder); > > @@ -1164,8 +1159,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > gen11_dsi_configure_transcoder(encoder, crtc_state); > > /* Step 4l: Gate DDI clocks */ > - if (DISPLAY_VER(dev_priv) == 11) > - gen11_dsi_gate_clocks(encoder); > + gen11_dsi_gate_clocks(encoder); > } > > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
On Tue, 09 Nov 2021, Jani Nikula <jani.nikula@intel.com> wrote: > On Tue, 09 Nov 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: >> This reverts commit 991d9557b0c457fb92bc49ddde24a7d9ce6144a8. >> The Bspec was updated recently with the pll ungate sequence >> similar to that of icl dsi enable sequence. >> Hence reverting. >> >> Bspec:49187 > > Please add a space after : in the Bspec tag, and please add a Fixes: tag > while applying. Pushed, thanks for the patch. BR, Jani. > >> >> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> > >> --- >> drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++-------- >> 1 file changed, 2 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c >> index 2337c0b54586..edc38fbd2545 100644 >> --- a/drivers/gpu/drm/i915/display/icl_dsi.c >> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c >> @@ -698,10 +698,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, >> intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); >> >> for_each_dsi_phy(phy, intel_dsi->phys) { >> - if (DISPLAY_VER(dev_priv) >= 12) >> - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); >> - else >> - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); >> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); >> } >> intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); >> >> @@ -1137,8 +1134,6 @@ static void >> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, >> const struct intel_crtc_state *crtc_state) >> { >> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> - >> /* step 4a: power up all lanes of the DDI used by DSI */ >> gen11_dsi_power_up_lanes(encoder); >> >> @@ -1164,8 +1159,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, >> gen11_dsi_configure_transcoder(encoder, crtc_state); >> >> /* Step 4l: Gate DDI clocks */ >> - if (DISPLAY_VER(dev_priv) == 11) >> - gen11_dsi_gate_clocks(encoder); >> + gen11_dsi_gate_clocks(encoder); >> } >> >> static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 2337c0b54586..edc38fbd2545 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -698,10 +698,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); for_each_dsi_phy(phy, intel_dsi->phys) { - if (DISPLAY_VER(dev_priv) >= 12) - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - else - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); @@ -1137,8 +1134,6 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - /* step 4a: power up all lanes of the DDI used by DSI */ gen11_dsi_power_up_lanes(encoder); @@ -1164,8 +1159,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, gen11_dsi_configure_transcoder(encoder, crtc_state); /* Step 4l: Gate DDI clocks */ - if (DISPLAY_VER(dev_priv) == 11) - gen11_dsi_gate_clocks(encoder); + gen11_dsi_gate_clocks(encoder); } static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
This reverts commit 991d9557b0c457fb92bc49ddde24a7d9ce6144a8. The Bspec was updated recently with the pll ungate sequence similar to that of icl dsi enable sequence. Hence reverting. Bspec:49187 Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-)