From patchwork Mon Nov 15 03:03:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Tseng X-Patchwork-Id: 12618611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EB48C433EF for ; Mon, 15 Nov 2021 03:03:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 529D961260 for ; Mon, 15 Nov 2021 03:03:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 529D961260 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D72C089A9F; Mon, 15 Nov 2021 03:03:27 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B670E89915 for ; Mon, 15 Nov 2021 03:03:26 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10168"; a="220257910" X-IronPort-AV: E=Sophos;i="5.87,235,1631602800"; d="scan'208";a="220257910" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2021 19:03:25 -0800 X-IronPort-AV: E=Sophos;i="5.87,235,1631602800"; d="scan'208";a="644693406" Received: from tsengwil-desk1.itwn.intel.com (HELO gar) ([10.5.253.7]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2021 19:03:24 -0800 From: William Tseng To: intel-gfx@lists.freedesktop.org Date: Mon, 15 Nov 2021 11:03:20 +0800 Message-Id: <20211115030320.26666-1-william.tseng@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211110102354.5640-1-william.tseng@intel.com> References: <20211110102354.5640-1-william.tseng@intel.com> Subject: [Intel-gfx] [PATCH v2] drm/i915/dsi: let HW maintain the HS-TRAIL timing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cooper Chiou , William Tseng Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This change is to avoid over-specification of the TEOT timing parameter, which is derived from software in current design. Supposed that THS-TRAIL and THS-EXIT have the minimum values, i.e., 60 and 100 in ns. If SW is overriding the HW default, the TEOT value becomes 150 ns, approximately calculated by the following formula. DIV_ROUND_UP(60/50)*50 + DIV_ROUND_UP(100/50))*50/2, where 50 is LP Escape Clock time in ns. The TEOT value 150 ns is larger than the maximum value, around 136 ns if UI is 1.8ns, (105 ns + 12*UI, defined by MIPI DPHY specification). However, the TEOT value will meet the specification if THS-TRAIL is set to the HW default, instead of software overriding. The timing change is made for both data lane and clock lane. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Lee Shawn C Cc: Cooper Chiou Signed-off-by: William Tseng --- drivers/gpu/drm/i915/display/icl_dsi.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 168c84a74d30..cd2f6ed51ed6 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1948,17 +1948,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) CLK_PRE_OVERRIDE | CLK_PRE(tclk_pre_cnt) | CLK_POST_OVERRIDE | - CLK_POST(tclk_post_cnt) | - CLK_TRAIL_OVERRIDE | - CLK_TRAIL(trail_cnt)); + CLK_POST(tclk_post_cnt)); /* data lanes dphy timings */ intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | HS_PREPARE(prepare_cnt) | HS_ZERO_OVERRIDE | HS_ZERO(hs_zero_cnt) | - HS_TRAIL_OVERRIDE | - HS_TRAIL(trail_cnt) | HS_EXIT_OVERRIDE | HS_EXIT(exit_zero_cnt));