| Message ID | 20211123193649.3153258-4-uma.shankar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable pipe color support on D13 platform | expand |
On Wed, Nov 24, 2021 at 01:06:49AM +0530, Uma Shankar wrote: > XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for > extended range. It has 511 entries for gamma with additional 2 entries > for extended range. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/i915_pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index f01cba4ec283..40d21a8c50ff 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -938,7 +938,7 @@ static const struct intel_device_info adl_s_info = { > > #define XE_LPD_FEATURES \ > .abox_mask = GENMASK(1, 0), \ > - .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \ > + .color = { .degamma_lut_size = 128, .gamma_lut_size = 513 }, \ Missing .degamma_lut_tests. Shouldn't .gamma_lut_size be 1024 or did they really change it? > .dbuf.size = 4096, \ > .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ > BIT(DBUF_S4), \ > -- > 2.25.1
> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Wednesday, November 24, 2021 8:28 PM > To: Shankar, Uma <uma.shankar@intel.com> > Cc: intel-gfx@lists.freedesktop.org; =ville.syrjala@linux.intel.com > Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/xelpd: Add Pipe Color Lut caps to > platform config > > On Wed, Nov 24, 2021 at 01:06:49AM +0530, Uma Shankar wrote: > > XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for > > extended range. It has 511 entries for gamma with additional 2 entries > > for extended range. > > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > > --- > > drivers/gpu/drm/i915/i915_pci.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c > > b/drivers/gpu/drm/i915/i915_pci.c index f01cba4ec283..40d21a8c50ff > > 100644 > > --- a/drivers/gpu/drm/i915/i915_pci.c > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > @@ -938,7 +938,7 @@ static const struct intel_device_info adl_s_info = > > { > > > > #define XE_LPD_FEATURES \ > > .abox_mask = GENMASK(1, 0), \ > > - .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \ > > + .color = { .degamma_lut_size = 128, .gamma_lut_size = 513 }, \ > > Missing .degamma_lut_tests. Yeah, will update this. > Shouldn't .gamma_lut_size be 1024 or did they really change it? Right, for 10bit gamma 1024 is the size as data is in 0.10 formats. It gets limited to 513 in case of logarithmic due to increased precision needing 2 register space for 1 entry. Thanks Ville for catching it, will fix this. Regards, Uma Shankar > > .dbuf.size = 4096, \ > > .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | > \ > > BIT(DBUF_S4), \ > > -- > > 2.25.1 > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index f01cba4ec283..40d21a8c50ff 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -938,7 +938,7 @@ static const struct intel_device_info adl_s_info = { #define XE_LPD_FEATURES \ .abox_mask = GENMASK(1, 0), \ - .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \ + .color = { .degamma_lut_size = 128, .gamma_lut_size = 513 }, \ .dbuf.size = 4096, \ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ BIT(DBUF_S4), \
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for extended range. It has 511 entries for gamma with additional 2 entries for extended range. Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)