From patchwork Mon Feb 21 14:16:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12753674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23F7DC433F5 for ; Mon, 21 Feb 2022 14:16:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FB2510E32A; Mon, 21 Feb 2022 14:16:41 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7EF1210E3E1; Mon, 21 Feb 2022 14:16:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645452997; x=1676988997; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lFGIImgHd6/ff58qxg2a/Fs06PSapnqmi056xJ7TBe0=; b=W+XlbStdcrsXHzI7+7e2sBhQPQzQC/tm8JDU4RlkgZdjRImRkxr7ZqcR gTYOIo9LOFddz71za0VmltznddNUfwjGZ71jGuUJ4lIcGka+mIflzw/sq 16WYtrSQaiz6B+KHJYp+Uv9VD4KCMy/LQEUSenbQNCe/alDg8rJZnHuUQ ozwY5lue/dEVuShTTIcLYnVks6F3pZf9lJzMO+/ZXHWXM4yhHnVjYwUuY OhzbY6DLsIeJpVqM40FD7UEpFrU8EVlH/nQBuLyA2UKPBBnrADwxgSwW/ H22ZyquthuUaV2Hg9oUKlsEXlPpR58nmkxoCRbDPqt3OuWZOq+y27viNw A==; X-IronPort-AV: E=McAfee;i="6200,9189,10264"; a="251467130" X-IronPort-AV: E=Sophos;i="5.88,385,1635231600"; d="scan'208";a="251467130" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2022 06:16:37 -0800 X-IronPort-AV: E=Sophos;i="5.88,385,1635231600"; d="scan'208";a="606400530" Received: from joeyegax-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.23.97]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2022 06:16:36 -0800 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Mon, 21 Feb 2022 14:16:15 +0000 Message-Id: <20220221141620.2490914-2-matthew.auld@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220221141620.2490914-1-matthew.auld@intel.com> References: <20220221141620.2490914-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t v2 1/6] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Thomas_Hellstr=C3=B6m?= , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For now dump into i915_drm_local.h. Once the uapi on the kernel side is merged, and is part of drm-next, we can sync the kernel headers and remove this. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- lib/i915/i915_drm_local.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h index 9e82c968..7b5285f3 100644 --- a/lib/i915/i915_drm_local.h +++ b/lib/i915/i915_drm_local.h @@ -21,6 +21,33 @@ extern "C" { */ #define I915_ENGINE_CLASS_COMPUTE 4 +/* + * Signal to the kernel that the object will need to be accessed via + * the CPU. + * + * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only + * strictly required on platforms where only some of the device memory + * is directly visible or mappable through the CPU, like on DG2+. + * + * One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to + * ensure we can always spill the allocation to system memory, if we + * can't place the object in the mappable part of + * I915_MEMORY_CLASS_DEVICE. + * + * Note that buffers that need to be captured with EXEC_OBJECT_CAPTURE, + * will need to enable this hint, if the object can also be placed in + * I915_MEMORY_CLASS_DEVICE, starting from DG2+. The execbuf call will + * throw an error otherwise. This also means that such objects will need + * I915_MEMORY_CLASS_SYSTEM set as a possible placement. + * + * Without this hint, the kernel will assume that non-mappable + * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the + * kernel can still migrate the object to the mappable part, as a last + * resort, if userspace ever CPU faults this object, but this might be + * expensive, and so ideally should be avoided. + */ +#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) + #if defined(__cplusplus) } #endif