From patchwork Fri Mar 18 19:55:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12785869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B7D3C433F5 for ; Fri, 18 Mar 2022 19:54:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC04B10E170; Fri, 18 Mar 2022 19:54:24 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F4B410E170 for ; Fri, 18 Mar 2022 19:54:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647633263; x=1679169263; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Scvi8WERYWWGDKF2/pHsfErdKOXjgKpiKPEQt/x9Q78=; b=ZV3avF4u/k2akmvbU/jg3jLnnUX25znTRdvHgfVrYE1KDpKaSgNfXd41 93YFQjC7ggyLgtSK2htHjeyVA7L1WfGbQGmbNrJ6JHQI0/9Tq2/yWkuGr pmpkFlBHrGYJjqHcYv00qp8dmKt31iKb04+U8cWOOhLRafFkpZ1QWGaab wePU/d1lYJDxWh1URU0XvbZRqeQc2wqAJ3bthMFyHgVxNE8JiwmJEf/rQ ASp2IfiMxjHK/ecgb8hSAoGH3v6zmglKAYWiWtqnosv5WDLFISCJEoPfZ gnq3OwtluIY5O6+zuIpOble30G+7B4gPddL/yE4lRuEvyASNnGGl4151i A==; X-IronPort-AV: E=McAfee;i="6200,9189,10290"; a="343648230" X-IronPort-AV: E=Sophos;i="5.90,192,1643702400"; d="scan'208";a="343648230" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2022 12:54:21 -0700 X-IronPort-AV: E=Sophos;i="5.90,192,1643702400"; d="scan'208";a="645658824" Received: from azahera-mobl2.amr.corp.intel.com (HELO josouza-mobl2.amr.corp.intel.com) ([10.212.1.248]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2022 12:54:20 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 18 Mar 2022 12:55:20 -0700 Message-Id: <20220318195522.456180-1-jose.souza@intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama B credits set by IFWI do not match with specification default, so here programming the right value. Also while at it, taking the oportunity to do a read-modify-write to all other bit in this register that specification don't ask us to change. BSpec: 49213 BSpec: 50343 Cc: Matt Roper Cc: Stanislav Lisovskiy Signed-off-by: Caz Yokoyama Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7cd586d280883..2e85ae575423a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1825,15 +1825,20 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - u32 val; + u32 val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe)); + val &= ~MBUS_DBOX_A_CREDIT_MASK; /* Wa_22010947358:adl-p */ if (IS_ALDERLAKE_P(dev_priv)) - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); else - val = MBUS_DBOX_A_CREDIT(2); + val |= MBUS_DBOX_A_CREDIT(2); - if (DISPLAY_VER(dev_priv) >= 12) { + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK); + if (IS_ALDERLAKE_P(dev_priv)) { + val |= MBUS_DBOX_BW_CREDIT(2); + val |= MBUS_DBOX_B_CREDIT(8); + } else if (DISPLAY_VER(dev_priv) >= 12) { val |= MBUS_DBOX_BW_CREDIT(2); val |= MBUS_DBOX_B_CREDIT(12); } else {