| Message ID | 20220413164351.48986-2-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] drm/i915/display/psr: Unset enable_psr2_sel_fetch if other checks in intel_psr2_config_valid() fails | expand |
On Wed, 2022-04-13 at 09:43 -0700, José Roberto de Souza wrote: > Alderlake-P don't have PSR2_MAN_TRK_CTL_ENABLE bit, instead it have > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE in the same bit but > this > bit is clearead after each vblank so we can't count on having it > set after planes are programmed. > > Cc: Jouni Högander <jouni.hogander@intel.com> > Fixes: 73262db68c27 ("drm/i915/display: Match PSR2 selective fetch > sequences with specification") > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 8ec7c161284be..84aeee63a3e80 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -565,16 +565,19 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > val |= EDP_PSR2_SU_SDP_SCANLINE; > > if (intel_dp->psr.psr2_sel_fetch_enabled) { > - u32 tmp; > - > /* Wa_1408330847 */ > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > intel_de_rmw(dev_priv, CHICKEN_PAR1_1, > DIS_RAM_BYPASS_PSR2_MAN_TRACK, > DIS_RAM_BYPASS_PSR2_MAN_TRACK); > > - tmp = intel_de_read(dev_priv, > PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); > - drm_WARN_ON(&dev_priv->drm, !(tmp & > PSR2_MAN_TRK_CTL_ENABLE)); > + if (!IS_ALDERLAKE_P(dev_priv)) { > + u32 tmp; > + > + tmp = intel_de_read(dev_priv, > + PSR2_MAN_TRK_CTL(intel_dp- > >psr.transcoder)); > + drm_WARN_ON(&dev_priv->drm, !(tmp & > PSR2_MAN_TRK_CTL_ENABLE)); > + } I think proper fix for this warning is to change PSR2_MAN_TRK_CTL_ENABLE to man_trk_ctl_partial_frame_bit_get()? Then we still need to figure out how to fix the original issue having this warning triggered. > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { > intel_de_write(dev_priv, > PSR2_MAN_TRK_CTL(intel_dp- > >psr.transcoder), 0); BR, Jouni Högander
On Thu, 2022-04-14 at 11:13 +0000, Hogander, Jouni wrote: > On Wed, 2022-04-13 at 09:43 -0700, José Roberto de Souza wrote: > > Alderlake-P don't have PSR2_MAN_TRK_CTL_ENABLE bit, instead it have > > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE in the same bit but > > this > > bit is clearead after each vblank so we can't count on having it > > set after planes are programmed. > > > > Cc: Jouni Högander <jouni.hogander@intel.com> > > Fixes: 73262db68c27 ("drm/i915/display: Match PSR2 selective fetch > > sequences with specification") > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++---- > > 1 file changed, 7 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 8ec7c161284be..84aeee63a3e80 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -565,16 +565,19 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > val |= EDP_PSR2_SU_SDP_SCANLINE; > > > > if (intel_dp->psr.psr2_sel_fetch_enabled) { > > - u32 tmp; > > - > > /* Wa_1408330847 */ > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > intel_de_rmw(dev_priv, CHICKEN_PAR1_1, > > DIS_RAM_BYPASS_PSR2_MAN_TRACK, > > DIS_RAM_BYPASS_PSR2_MAN_TRACK); > > > > - tmp = intel_de_read(dev_priv, > > PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); > > - drm_WARN_ON(&dev_priv->drm, !(tmp & > > PSR2_MAN_TRK_CTL_ENABLE)); > > + if (!IS_ALDERLAKE_P(dev_priv)) { > > + u32 tmp; > > + > > + tmp = intel_de_read(dev_priv, > > + PSR2_MAN_TRK_CTL(intel_dp- > > > psr.transcoder)); > > + drm_WARN_ON(&dev_priv->drm, !(tmp & > > PSR2_MAN_TRK_CTL_ENABLE)); > > + } > > I think proper fix for this warning is to change > PSR2_MAN_TRK_CTL_ENABLE to man_trk_ctl_partial_frame_bit_get()? Then we > still need to figure out how to fix the original issue having this > warning triggered. For TGL I believe that PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE will be cleared at vblanks but I don't have a TGL with eDP panel to test it. Will leave the current code as it and bring the state cleanup on PSR disable patch. > > > > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { > > intel_de_write(dev_priv, > > PSR2_MAN_TRK_CTL(intel_dp- > > > psr.transcoder), 0); > > BR, > > Jouni Högander
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8ec7c161284be..84aeee63a3e80 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -565,16 +565,19 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_SU_SDP_SCANLINE; if (intel_dp->psr.psr2_sel_fetch_enabled) { - u32 tmp; - /* Wa_1408330847 */ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, DIS_RAM_BYPASS_PSR2_MAN_TRACK); - tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); - drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); + if (!IS_ALDERLAKE_P(dev_priv)) { + u32 tmp; + + tmp = intel_de_read(dev_priv, + PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); + drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); + } } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
Alderlake-P don't have PSR2_MAN_TRK_CTL_ENABLE bit, instead it have ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE in the same bit but this bit is clearead after each vblank so we can't count on having it set after planes are programmed. Cc: Jouni Högander <jouni.hogander@intel.com> Fixes: 73262db68c27 ("drm/i915/display: Match PSR2 selective fetch sequences with specification") Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-)