| Message ID | 20220413192730.3608660-11-umesh.nerlige.ramappa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable compute and related WAs for DG2 | expand |
On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote: > From: John Harrison <John.C.Harrison@Intel.com> > > The above two workaronuds regarding context isolation are implemented workaronuds -> workarounds > by GuC. The KMD just needs to enable them. > > v2: Use dg2 stepping for ctx isolation WA (Umesh) > v3: Rebase (Umesh) > v4: Fix WA comments (Daniele) > v5: Drop Wa_22012727685 for G10 as it is n/a > v6: Undo v5 change since the G10 condition is needed > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8 ++++++++ > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index 228070e31ef0..2c4ad4a65089 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -319,6 +319,14 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) > IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) > flags |= GUC_WA_RCS_RESET_BEFORE_RC6; > > + /* > + * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..) > + * Wa_22012727685:dg2_g11[a0..) > + */ > + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || > + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER)) > + flags |= GUC_WA_CONTEXT_ISOLATION; > + > return flags; > } > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > index e389a3a041a2..42cb7a9a6199 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > @@ -101,6 +101,7 @@ > #define GUC_WA_GAM_CREDITS BIT(10) > #define GUC_WA_DUAL_QUEUE BIT(11) > #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13) > +#define GUC_WA_CONTEXT_ISOLATION BIT(15) > #define GUC_WA_PRE_PARSER BIT(14) > #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17) > #define GUC_WA_POLLCS BIT(18)
On Thu, Apr 14, 2022 at 05:22:47PM -0700, John Harrison wrote: >On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote: >>From: John Harrison <John.C.Harrison@Intel.com> >> >>The above two workaronuds regarding context isolation are implemented >workaronuds -> workarounds > >>by GuC. The KMD just needs to enable them. >> >>v2: Use dg2 stepping for ctx isolation WA (Umesh) >>v3: Rebase (Umesh) >>v4: Fix WA comments (Daniele) >>v5: Drop Wa_22012727685 for G10 as it is n/a >>v6: Undo v5 change since the G10 condition is needed >> >>Signed-off-by: John Harrison <John.C.Harrison@Intel.com> with spelling corrected above, this is Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Umesh >>--- >> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8 ++++++++ >> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 + >> 2 files changed, 9 insertions(+) >> >>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c >>index 228070e31ef0..2c4ad4a65089 100644 >>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c >>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c >>@@ -319,6 +319,14 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) >> IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) >> flags |= GUC_WA_RCS_RESET_BEFORE_RC6; >>+ /* >>+ * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..) >>+ * Wa_22012727685:dg2_g11[a0..) >>+ */ >>+ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || >>+ IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER)) >>+ flags |= GUC_WA_CONTEXT_ISOLATION; >>+ >> return flags; >> } >>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h >>index e389a3a041a2..42cb7a9a6199 100644 >>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h >>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h >>@@ -101,6 +101,7 @@ >> #define GUC_WA_GAM_CREDITS BIT(10) >> #define GUC_WA_DUAL_QUEUE BIT(11) >> #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13) >>+#define GUC_WA_CONTEXT_ISOLATION BIT(15) >> #define GUC_WA_PRE_PARSER BIT(14) >> #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17) >> #define GUC_WA_POLLCS BIT(18) >
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 228070e31ef0..2c4ad4a65089 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -319,6 +319,14 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) flags |= GUC_WA_RCS_RESET_BEFORE_RC6; + /* + * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..) + * Wa_22012727685:dg2_g11[a0..) + */ + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER)) + flags |= GUC_WA_CONTEXT_ISOLATION; + return flags; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h index e389a3a041a2..42cb7a9a6199 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h @@ -101,6 +101,7 @@ #define GUC_WA_GAM_CREDITS BIT(10) #define GUC_WA_DUAL_QUEUE BIT(11) #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13) +#define GUC_WA_CONTEXT_ISOLATION BIT(15) #define GUC_WA_PRE_PARSER BIT(14) #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17) #define GUC_WA_POLLCS BIT(18)