From patchwork Mon Apr 18 10:54:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12816484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D29EC433F5 for ; Mon, 18 Apr 2022 10:54:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0404F10F584; Mon, 18 Apr 2022 10:54:38 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5FF3010F582 for ; Mon, 18 Apr 2022 10:54:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1650279275; x=1681815275; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AhQNzAHAU4k1A9ssUslI/owF+XXEY1s/dpk0Ht2gesU=; b=dZy+GYdXAxuNfKioPMxeY773FNjDRO1anL5tgbTurCb4DobPbKbjlrT7 jhouiGNzhpFdYs9x8PaeGaRMcQYR0BzLzdV/4mBBrmiMNHmJBrqLwCH5m 9GEl1G45GbM2EV2g7xvGA2OyIqmtPMjZ9DFJlAPRmRih7PStxLWRu078z mdMpk5aCGAI0csvY8o+iEybZXnDGz7lnZ7pTkWdrxfkQxgNrRu8aCkRnP JgP5zvgYIq+A2x+eh6bKdYvwJKz82NG9kvDy3TJjuoIEWYyaZ9f/kfIWD KZE4D4emUxpk6teTcIx3L0VqqedlUKoPpEAkj784puN4mdKcOpD4GKVz/ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10320"; a="250798271" X-IronPort-AV: E=Sophos;i="5.90,269,1643702400"; d="scan'208";a="250798271" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2022 03:54:35 -0700 X-IronPort-AV: E=Sophos;i="5.90,269,1643702400"; d="scan'208";a="665139389" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2022 03:54:32 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Mon, 18 Apr 2022 16:24:06 +0530 Message-Id: <20220418105408.13444-5-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220418105408.13444-1-anshuman.gupta@intel.com> References: <20220418105408.13444-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 4/6] drm/i915/opregion: Cond dgfx opregion func registration X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, lucas.demarchi@intel.com, rodrigo.vivi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DGFX ASLS and OPROM OpRegion are only supported on the GFX Cards, which supports Display Engine. Register opregion function accordingly using the HAS_DISPLAY(). And early return intel_opregion_setup() if no opregion func to avoid NULL pointer oops. v2: - Change the commit log. v3: - Use nested condition for IS_DGFX() and HAS_DISPLAY(). [Jani] Cc: Badal Nilawar Cc: Jani Nikula Cc: Uma Shankar Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 6bba0e2cff72..8e5960ec30de 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -894,6 +894,9 @@ static int intel_opregion_setup(struct drm_i915_private *dev_priv) BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100); BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400); + if (!opregion->opregion_func) + return 0; + INIT_WORK(&opregion->asle_work, asle_work); base = opregion->opregion_func->alloc_opregion(dev_priv); @@ -1348,10 +1351,12 @@ int intel_opregion_init(struct drm_i915_private *i915) { struct intel_opregion *opregion = &i915->opregion; - if (IS_DGFX(i915)) - opregion->opregion_func = &dgfx_opregion_func; - else + if (IS_DGFX(i915)) { + if (HAS_DISPLAY(i915)) + opregion->opregion_func = &dgfx_opregion_func; + } else { opregion->opregion_func = &igfx_opregion_func; + } return intel_opregion_setup(i915); }