From patchwork Wed May 4 19:07:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12838423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D088BC433FE for ; Wed, 4 May 2022 19:07:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A66110E7CF; Wed, 4 May 2022 19:07:21 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8FFED10E77B for ; Wed, 4 May 2022 19:07:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651691240; x=1683227240; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JxS/VPXz5MoOGj8XbNAuHM315Xk9EoFWpBx7duN7CUY=; b=g/liYE5QTLKFGZfI1maBjzWfNUv8d42GEfJos6Zr523dAUluMX/n9Z8f lmTB2cF7fBRYGIZsbsYOaasNCb7HztgudOPVn9nRrZVejSIvu7rcGykvE QjxSMu/VN8QHKXVi4WtmaTuUI9VKiBHcbEOkLJmFmKP69WskNq1rOYalv uEh89gD04yOtqq+lg1izNTIUEAMnaH7tZA3+S9AnJer2cvWDz0lfrbQQn f7UtF3dnRrDEpravd3Z5LgxaA6s4ZZ3Zo16xBP4GLNPP5gSTWVEXrvyaE ETDeAx+6fiTrHqODNHxE+JnLYym4MWQ2aLlYLnEqB1iDA4Jwhg+Is2KLC A==; X-IronPort-AV: E=McAfee;i="6400,9594,10337"; a="249854481" X-IronPort-AV: E=Sophos;i="5.91,199,1647327600"; d="scan'208";a="249854481" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2022 12:07:20 -0700 X-IronPort-AV: E=Sophos;i="5.91,199,1647327600"; d="scan'208";a="517162833" Received: from unknown (HELO josouza-mobl2.fso.intel.com) ([10.230.18.139]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2022 12:07:19 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 4 May 2022 12:07:49 -0700 Message-Id: <20220504190756.466270-5-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504190756.466270-1-jose.souza@intel.com> References: <20220504190756.466270-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/12] drm/i915: Drop has_rc6p from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as it was only supported in graphics version 6 and 7 not including haswell. Signed-off-by: José Roberto de Souza Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_pci.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d29dca83185ac..602e056edd314 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1310,7 +1310,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, /* ilk does support rc6, but we do not implement [power] contexts */ #define HAS_RC6(dev_priv) (GRAPHICS_VER(dev_priv) >= 6) -#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) +#define HAS_RC6p(dev_priv) (GRAPHICS_VER(dev_priv) >= 6 && \ + GRAPHICS_VER(dev_priv) <= 7 && \ + !IS_HASWELL(dev_priv)) #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 90584c462f225..516f28d4db611 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -405,7 +405,6 @@ static const struct intel_device_info ilk_m_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .has_rc6p = 1, \ .has_rps = true, \ .dma_mask_size = 40, \ .ppgtt_type = INTEL_PPGTT_ALIASING, \ @@ -455,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .has_rc6p = 1, \ .has_reset_engine = true, \ .has_rps = true, \ .dma_mask_size = 40, \ @@ -540,7 +538,6 @@ static const struct intel_device_info vlv_info = { .display.has_ddi = 1, \ .display.has_fpga_dbg = 1, \ .display.has_dp_mst = 1, \ - .has_rc6p = 0 /* RC6p removed-by HSW */, \ HSW_PIPE_OFFSETS, \ .has_runtime_pm = 1 diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index b3244170c4638..599cb265946b8 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -156,7 +156,6 @@ enum intel_ppgtt_type { func(has_mslices); \ func(has_pooled_eu); \ func(has_pxp); \ - func(has_rc6p); \ func(has_rps); \ func(has_runtime_pm); \ func(has_snoop); \