| Message ID | 20220504190756.466270-8-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/12] drm/i915: Drop IPC from display 13 and newer | expand |
On Wed, May 04, 2022 at 12:07:52PM -0700, José Roberto de Souza wrote: > No need to have this parameter in intel_device_info struct > as all platforms with display version 9 or newer, haswell or broadwell > supports it. > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 +++- > drivers/gpu/drm/i915/i915_pci.c | 3 --- > drivers/gpu/drm/i915/intel_device_info.h | 1 - > 3 files changed, 3 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f23e5c5cbf82b..a354815445238 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1299,7 +1299,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) > > #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) > -#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) > +#define HAS_DDI(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || \ > + IS_HASWELL(dev_priv) || \ > + IS_BROADWELL(dev_priv)) Technically the order of broadwell and haswell should be reversed here (if we're going from newest to oldest). Aside from that, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) > #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > #define HAS_PSR_HW_TRACKING(dev_priv) \ > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 25aa8f5957f1e..96270c0ddf06c 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -533,7 +533,6 @@ static const struct intel_device_info vlv_info = { > .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ > .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ > - .display.has_ddi = 1, \ > .display.has_fpga_dbg = 1, \ > .display.has_dp_mst = 1, \ > HSW_PIPE_OFFSETS, \ > @@ -679,7 +678,6 @@ static const struct intel_device_info skl_gt4_info = { > BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ > BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ > .has_64bit_reloc = 1, \ > - .display.has_ddi = 1, \ > .display.has_fpga_dbg = 1, \ > .display.fbc_mask = BIT(INTEL_FBC_A), \ > .display.has_hdcp = 1, \ > @@ -926,7 +924,6 @@ static const struct intel_device_info adl_s_info = { > .dbuf.size = 4096, \ > .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ > BIT(DBUF_S4), \ > - .display.has_ddi = 1, \ > .display.has_dmc = 1, \ > .display.has_dp_mst = 1, \ > .display.has_dsc = 1, \ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 7cf16b0315b54..d809d44098c63 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -166,7 +166,6 @@ enum intel_ppgtt_type { > func(cursor_needs_physical); \ > func(has_cdclk_crawl); \ > func(has_dmc); \ > - func(has_ddi); \ > func(has_dp_mst); \ > func(has_dsc); \ > func(has_fpga_dbg); \ > -- > 2.36.0 >
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f23e5c5cbf82b..a354815445238 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1299,7 +1299,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) -#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) +#define HAS_DDI(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || \ + IS_HASWELL(dev_priv) || \ + IS_BROADWELL(dev_priv)) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) #define HAS_PSR_HW_TRACKING(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 25aa8f5957f1e..96270c0ddf06c 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -533,7 +533,6 @@ static const struct intel_device_info vlv_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ - .display.has_ddi = 1, \ .display.has_fpga_dbg = 1, \ .display.has_dp_mst = 1, \ HSW_PIPE_OFFSETS, \ @@ -679,7 +678,6 @@ static const struct intel_device_info skl_gt4_info = { BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ .has_64bit_reloc = 1, \ - .display.has_ddi = 1, \ .display.has_fpga_dbg = 1, \ .display.fbc_mask = BIT(INTEL_FBC_A), \ .display.has_hdcp = 1, \ @@ -926,7 +924,6 @@ static const struct intel_device_info adl_s_info = { .dbuf.size = 4096, \ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ BIT(DBUF_S4), \ - .display.has_ddi = 1, \ .display.has_dmc = 1, \ .display.has_dp_mst = 1, \ .display.has_dsc = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 7cf16b0315b54..d809d44098c63 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -166,7 +166,6 @@ enum intel_ppgtt_type { func(cursor_needs_physical); \ func(has_cdclk_crawl); \ func(has_dmc); \ - func(has_ddi); \ func(has_dp_mst); \ func(has_dsc); \ func(has_fpga_dbg); \
No need to have this parameter in intel_device_info struct as all platforms with display version 9 or newer, haswell or broadwell supports it. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_pci.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-)