@@ -84,6 +84,11 @@
* use page flips.
*/
+#define HAS_PSR_HW_TRACKING(dev_priv) ((DISPLAY_VER(dev_priv) >= 9 && \
+ DISPLAY_VER(dev_priv) <= 11) || \
+ IS_TIGERLAKE(dev_priv) || \
+ IS_DG1(dev_priv))
+
static bool psr_global_enabled(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1308,8 +1308,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DP_MST(dev_priv) (HAS_DDI(dev_priv))
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
#define HAS_PSR(dev_priv) (DISPLAY_VER(dev_priv) >= 9)
-#define HAS_PSR_HW_TRACKING(dev_priv) \
- (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
@@ -629,7 +629,6 @@ static const struct intel_device_info chv_info = {
GEN9_DEFAULT_PAGE_SIZES, \
.display.has_dmc = 1, \
.display.has_hdcp = 1, \
- .display.has_psr_hw_tracking = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.slice_mask = BIT(DBUF_S1)
@@ -677,7 +676,6 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_fpga_dbg = 1, \
.display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_hdcp = 1, \
- .display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
.display.has_dmc = 1, \
.has_rps = true, \
@@ -863,7 +861,6 @@ static const struct intel_device_info rkl_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C),
.display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
};
@@ -894,7 +891,6 @@ static const struct intel_device_info adl_s_info = {
PLATFORM(INTEL_ALDERLAKE_S),
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.dma_mask_size = 39,
@@ -952,7 +948,6 @@ static const struct intel_device_info adl_p_info = {
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
.display.has_cdclk_crawl = 1,
.display.has_modular_fia = 1,
- .display.has_psr_hw_tracking = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
@@ -173,7 +173,6 @@ enum intel_ppgtt_type {
func(has_hti); \
func(has_modular_fia); \
func(has_overlay); \
- func(has_psr_hw_tracking); \
func(overlay_needs_physical); \
func(supports_tv);
No need to have this parameter in intel_device_info struct as this feature was only supported by display 9, 10 and 11, tigerlake and DG1, no newer platforms will have this feature. While at it also moving it to intel_psr.c as this is the only place were it is used. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. v2: - moved macro to intel_psr.c Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++ drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/i915/i915_pci.c | 5 ----- drivers/gpu/drm/i915/intel_device_info.h | 1 - 4 files changed, 5 insertions(+), 8 deletions(-)