diff mbox series

[2/7] drm/i915/dg1: OpRegion PCON DG1 MBD config support

Message ID 20220518130716.10936-3-anshuman.gupta@intel.com (mailing list archive)
State New, archived
Headers show
Series DG2 VRAM_SR Support | expand

Commit Message

Gupta, Anshuman May 18, 2022, 1:07 p.m. UTC 
DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.

i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
VRSR.

BSpec: 53440
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 36 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_opregion.h |  6 ++++
 2 files changed, 42 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index a728f4c2f532..3dcd54517b89 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@ 
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DG1_MBD_CONFIG				BIT(9)
+#define PCON_DG1_MBD_CONFIG_FIELD_VALID			BIT(10)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
 
@@ -1242,6 +1244,37 @@  void intel_opregion_unregister(struct drm_i915_private *i915)
 	opregion->lid_state = NULL;
 }
 
+static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!IS_DG1(i915))
+		return false;
+
+	if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
+		return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
+	else
+		return false;
+}
+
+/**
+ * intel_opregion_vram_sr_required().
+ * @i915 i915 device priv data.
+ * It returns a boolean whether opregion vram_sr support
+ * is required.
+ */
+bool
+intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	if (!IS_DGFX(i915))
+		return false;
+
+	if (IS_DG1(i915))
+		return intel_opregion_dg1_mbd_config(i915);
+
+	return false;
+}
+
 /*
  * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
  * Refresh capability support.
@@ -1269,6 +1302,9 @@  void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
 {
 	struct intel_opregion *opregion = &i915->opregion;
 
+	if (!intel_opregion_vram_sr_required(i915))
+		return;
+
 	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 0aa1c4a8a482..a74686aa3cc3 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -77,6 +77,7 @@  int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
 bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
 void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
+bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
 
 #else /* CONFIG_ACPI*/
 
@@ -138,6 +139,11 @@  static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
 {
 }
 
+static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	return false;
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif